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Preliminary Data Sheet July 2001
ORCA(R) ORT82G5 1.0--1.25/2.0--2.5/3.125 Gbits/s Backplane Interface FPSC
Introduction
Agere Systems Inc. has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips (SoC) architecture, the ORT82G5 is made up of backplane transceivers containing eight channels, each operating at up to 3.125 Gbits/s (2.5 Gbits/s data rate), with a fullduplex synchronous interface with built-in clock and data recovery (CDR), along with up to 400k usable FPGA system gates. The CDR circuitry is a macrocell available from Agere's smart silicon macro library, and has already been implemented in numerous applications including ASICs, standard products, and FPSCs to create interfaces for SONET/SDH, STS-48/STM-16, STS-192/STM-64, and 10 Gbit Ethernet applications. With the addition of protocol and access logic such as protocol-independent framers, asynchronous transfer mode (ATM) framers, packet-over-SONET (POS) interfaces, and framers for HDLC for Internet protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/ SDH based. For example, designers can build a 20 Gbits/s bridge for 10 Gbits/s Ethernet; the highspeed SERDES interfaces can comprise two XAUI interfaces with configurable back-end interfaces such as XGMII or POS-PHY4. The ORT82G5 can also be used to provide a full 10 Gbits/s backplane data connection with protection between a line card and switch fabric. The ORT82G5 offers a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT82G5 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device.The first version of the device supports 8b/10b encoding/decoding and link state machines for Ethernet, fibre-channel, and InfiniBandTM. Version II adds SONET data scrambling/descrambling, streamlined SONET framing, transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. Version II adds decimation and interpolation for connections at 622 Mbits/s rates.
Table 1. ORCA ORT82G5 Family--Available FPGA Logic Device ORT82G5 PFU Rows 36 PFU Columns 36 Total PFUs 1296 User I/O 372/432 LUTs 10,368 EBR Blocks 12 EBR Bits Usable Gates (k) (k) 111 380--800
The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count to a gate count assuming that 20% of the PFUs/SLICs are being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calculations. 372 user I/Os out of a total of 432 user I/Os are bonded in the 680 PBGAM package.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Table of Contents
Contents Page Contents Page
Introduction..................................................................1 Embedded Function Features .....................................4 Intellectual Property Features......................................4 Programmable Features..............................................5 Programmable Logic System Features .......................6 Description...................................................................7 What Is an FPSC? ....................................................7 FPSC Overview .........................................................7 FPSC Gate Counting ................................................7 FPGA/Embedded Core Interface ..............................7 ORCA Foundry 2000 Development System .............7 FPSC Design Kit .......................................................8 FPGA Logic Overview ...............................................8 PLC Logic ..................................................................8 Programmable I/O .....................................................9 Routing ......................................................................9 System-Level Features..............................................10 Microprocessor Interface .........................................10 System Bus .............................................................10 Phase-Locked Loops ..............................................10 Embedded Block RAM ............................................10 Configuration ...........................................................11 Additional Information .............................................11 ORT82G5 Overview ..................................................11 Device Layout .........................................................11 Backplane Transceiver Interface .............................11 ORT82G5 Overview (continued) ...............................12 Serializer and Deserializer (SERDES) ....................14 MUX/DeMUX Block .................................................14 Multichannel Alignment FIFOs ................................14 XAUI or Fibre-Channel Link State Machine ............14 Dual Port RAMs ......................................................14 FPGA Interface .......................................................15 FPSC Configuration ................................................15 Backplane Transceiver Core Detailed Description ....15 SERDES .................................................................15 SERDES Transmit Path (FPGA AE Backplane) ......18 Transmit Preemphasis and Amplitude Control ........19 SERDES Receive Path (Backplane AE FPGA) .......19 8b/10b Encoding/Decoding .....................................21
SERDES Transmit and Receive PLLs ................... 21 Reference Clock ..................................................... 21 Byte Alignment ....................................................... 22 Link State Machines ............................................... 22 XAUI Link Synchronization Function ...................... 23 MUX/DeMUX Block ................................................ 25 Multichannel Alignment (Backplane AE FPGA) ....... 27 Alignment Sequence .............................................. 29 Loopback Modes .................................................... 32 High-Speed Serial Loopback .................................. 32 Parallel Loopback at the SERDES Boundary ......... 33 Parallel Loopback at MUX/DeMUX Boundary Excluding SERDES ............................................... 33 ASB Memory Blocks ............................................... 34 Memory Map............................................................. 36 Definition of Register Types ................................... 36 Absolute Maximum Ratings...................................... 54 Recommended Operating Conditions ...................... 54 HSI Electrical and Timing Characteristics ................ 54 Pin Information ......................................................... 57 Power Supplies for ORT82G5 ................................ 63 Recommended Power Supply Connections ........... 64 Recommended Power Supply Filtering Scheme .... 64 Package Pinouts .................................................... 69 Pin Information ......................................................... 70 Package Thermal Characteristics Summary.................................................................. 87 JA ......................................................................... 87 JC ........................................................................ 87 JC ........................................................................ 87 JB ........................................................................ 87 FPSC Maximum Junction Temperature ................. 87 Package Thermal Characteristics............................. 88 Package Coplanarity ................................................ 88 Package Parasitics ................................................... 88 Package Outline Diagrams....................................... 89 Terms and Definitions ............................................ 89 680-Pin PBGAM ..................................................... 90 Hardware Ordering Information ................................ 91 Software Ordering Information ................................. 91
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Table of Contents
List of Figures Page List of Tables Page
Figure 1. ORT82G5 Block Diagram ..........................12 Figure 2. Internal High-Level Diagram of ORT82G5 Transceiver ..............................................................13 Figure 3. SERDES Functional Block Diagram for One Channel ...........................................................17 Figure 4. ORT82G5 Transmit Path for a Single SERDES Channel ...................................................18 Figure 5. ORT82G5 Receive Path for a Single SERDES Channel ...................................................20 Figure 6. Fibre-Channel Link State Machine State Diagram ...................................................................22 Figure 7. XAUI Link Synchronization State Diagram ...................................................................24 Figure 8. Transmit MUX Block for a Single SERDES Channel ...................................................................25 Figure 9. Receive DeMUX Block for a Single SERDES Channel ...................................................26 Figure 10. Interconnect of Streams for FIFO ............27 Figure 11. Example of SERDES A Alignment and ...27 Figure 12. Example of SERDES A and B Alignment ................................................................27 Figure 13. Example of Multiple Twin Channel ..........27 Figure 14. Multichannel Alignment FIFO Block for a Single SERDES Channel .....................................28 Figure 15. De-Skew Lanes by Aligning /A/ Columns ..................................................................30 Figure 16. Block Diagram of Memory Block .............34 Figure 17. Minimum Timing Specs for Memory Blocks-Write Cycle ..................................................35 Figure 18. Minimum Timing Specs for Memory Blocks-Read Cycle ..................................................35 Figure 19. Receive Data Eye-diagram Template (Differential) .............................................................55 Figure 20. Power Supply Filtering ............................65 Figure 21. Package Parasitics ..................................88
Table 1. ORCA ORT82G5 Family--Available FPGA Logic ...............................................................1 Table 2. Preemphasis Settings ...................................19 Table 3. Transmit PLL Clock and Data Rates ............21 Table 4. Receive PLL Clock and Data Rates .............21 Table 5. XAUI Link Synchronization State Diagram Notation--Variables ..................................23 Table 6. XAUI Link Synchronization State Diagram--Functions ................................................23 Table 7. Multichannel Alignment Modes .....................29 Table 8. Definition of Bits of MRWDxy[39:0] ...............31 Table 9. High-Speed Serial Loopback Configuration .32 Table 10. Parallel Loopback Configuration .................33 Table 11. Structural Register Elements ......................36 Table 12. Memory Map ...............................................37 Table 13. Absolute Maximum Ratings ........................54 Table 14. Recommended Operating Conditions ........54 Table 15. Absolute Maximum Ratings ........................54 Table 16. Recommended Operating Conditions ........54 Table 17. Receiver Specifications ..............................55 Table 18. Reference Clock Specifications (REFINP and REFINN) ............................................56 Table 19. Channel Output Jitter (1.25 Gbits/s) ...........56 Table 20. Channel Output Jitter (2.5 Gbits/s) .............56 Table 21. Serial Output Timing Levels (CML I/O) .......56 Table 22. Serial Input Timing and Levels (CML I/O) ...56 Table 23. FPGA Common-Function Pin Description ..57 Table 24. FPSC Function Pin Description ..................60 Table 25. Power Supply Pin Groupings ......................63 Table 26. Embedded Core/FPGA Interface Signal Description ...................................................66 Table 27. ORT82G5 680-Pin PBGAM Pinout .............70 Table 28. ORCA ORT82G5 Plastic Package Thermal Guidelines .................................................88 Table 29. ORCA ORT82G5 Package Parasitics ........88 Table 30. Device Type Options ..................................91 Table 31. Temperature Options ..................................91 Table 32. Package Type Options ...............................91 Table 33. ORCA FPSC Package Matrix (Speed Grades) .......................................................91
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Embedded Function Features
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High-speed SERDES programmable serial data rates of 622 Mbits/s (SONET only), 1.25 Gbits/s, 2.5 Gbits/s, and 3.125 Gbits/s. Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock per quad channels (separate PLL per channel). Ability to select full-rate or half-rate operation per Tx or Rx channel by setting the appropriate control registers. Transmit preemphasis (programmable) for improved receive data eye opening. Receiver energy detector to determine if a link is active. 32-bit (SONET or 8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic. Provides a 10 Gbits/s backplane interface to switch fabric with protection. Also supports port cards at 622 Mbits/s or 2.5 Gbits/s. 3.125 Gbits/s SERDES compliant with XAUI serial data specification for 10 Gbit Ethernet applications with protection. Most XAUI features for 10 Gbit Ethernet are embedded including the required link state machine. Compliant to fibre-channel physical layer specification. Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed backplane data transfer. No knowledge of SONET/SDH needed in generic applications. Simply supply data, a 100 MHz-- 156.25 MHz reference clock, and, optionally, a frame pulse. High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. Eight-channel HSI function provides 2.5 Gbits/s serial user data interface per channel for a total chip bandwidth of 20 Gbits/s (full duplex). SERDES has low-power CML buffers. Support for 1.5 V/1.8 V I/Os. Programmable STS-12 or STS-48 framing in SONET mode per channel (in version II). OC-192 framing in quad OC-48 (four channels) also supported. Powerdown option of SERDES HSI receiver on a per-channel basis. Selectable 8b/10b coder/decoder or SONET scrambler/descrambler (added for version 2).
SERDES HSI automatically recovers from loss-ofclock once its reference clock returns to normal operating state. In-band management and configuration through transport overhead extraction/insertion in SONET mode (version II). Supports transparent mode where the only insertion is A1/A2 framing bytes in SONET mode (version II). Built-in boundary scan (IEEE (R) 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES interface. FIFOs align incoming data across all eight channels (all eight channels, two groups of four channels, or four groups of two channels). Alignment is done using comma characters or /A/ in 8b/10b mode or frame pulse in SONET mode (version II). Optional ability to bypass alignment FIFOs for asynchronous operation between channels. (Each channel includes its own clock and frame pulse or comma detect.) Frame alignment across multiple ORT82G5 devices for work/protect switching at STS-768/STM256 and above rates in SONET mode. Addition of two 4K X 36 dual-port RAMs with access to the programmable logic.
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Intellectual Property Features
Programmable logic provides a variety of yet-to-be standardized interface functions, including the following Agere ME IP core functions:
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10 Gbits/s Ethernet as defined by IEEE 802.3ae: -- XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short reach (typically less than 2") interconnect interface. -- X58+ X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet. -- 64b/66b encoders/decoders for 10 Gbits/s Ethernet. -- XAUI to XGMII translator, including dual XAUI protection. POS-PHY4 interface for 10 Gbits/s SONET/SDH and OTN systems and some 10 Gbits/s Ethernet systems to allow easy integration of InfiniBand, fibre-channel, and 10 Gbits/s Ethernet in data over fibre applications. Ethernet MAC functions at 10/100 Mbits/s, 1 Gbits/s, and 10 Gbits/s. Other functions such as fibre-channel and InfiniBand link layer IP cores are also going to be developed. Agere Systems Inc.
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
-- 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. -- Flexible fast access to PFU inputs from routing. -- Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
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Programmable Features
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High-performance programmable logic: -- 0.13 m 7-level metal technology. -- Internal performance of >250 MHz. -- Over 400k usable system gates. -- Meets multiple I/O interface standards. -- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. Traditional I/O selections: -- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. -- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. -- Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. -- Two slew rates supported (fast and slew-limited). -- Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. -- Fast open-drain drive capability. -- Capability to register 3-state enable signal. -- Off-chip clock drive capability. -- Two-input function generator in output path. New programmable high-speed I/O: -- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR. -- Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable, parallel termination (100 ) is also supported for these I/Os. -- Customer defined: ability to substitute arbitrary standard cell I/O to meet fast-moving standards. New capability to (de)multiplex I/O signals: -- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate). -- New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). Enhanced twin-quad programmable function unit (PFU): -- Eight 16-bit look-up tables (LUTs) per PFU. -- Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. -- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. -- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU.
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Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PALTM-like and-or-invert (AOI) in each programmable logic cell. New 200 MHz embedded quad-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as: -- 1--512 x 18 (quad-port, two read/two write) with optional built in arbitration. -- 1--256 x 36 (dual-port, one read/one write). -- 1--1k x 9 (dual-port, one read/one write). -- 2--512 x 9 (dual-port, one read/one write for each). -- 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). -- Supports joining of RAM blocks. -- Two 16 x 8-bit content addressable memory (CAM) support. -- FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. -- Constant multiply (8 x 16 or 16 x 8). -- Dual variable multiply (8 x 8). Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 66 MHz bus performance. Included are built-in system registers that act as the control and status center for the device.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Programmable Features (continued)
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Built-in testability: -- Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). -- Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. -- TS_ALL testability function to 3-state all I/O pins. -- New temperature-sensing diode. Improved built-in clock management with programmable phase-locked loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
Flexible general purpose PPLLs offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E4). New local clock routing structures allow creation of localized clock trees. New double-data rate (DDR) and zero-bus turnaround (ZBT) memory interfaces support the latest high-speed memory interfaces. New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. ORCA Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3; as well as POS-PHY3. Also meets proposed specifications for UTOPIA Level 4 and POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-over-SONET as defined by the Saturn Group. Two new edge clock routing structures allow up to seven high-speed clocks on each edge of the device for improved setup/hold and clock to out performance.
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Programmable Logic System Features
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PCI local bus compliant for FPGA I/Os. Improved PowerPC (R)860 and PowerPC II highspeed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. New embedded AMBA TM specification 2.0 AHB system bus (ARM (R) processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications.
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
number of interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the ORCA Foundry Development System. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multimaster 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions including the embedded block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
Description
What Is an FPSC?
FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs.
FPSC Overview
Agere's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed--all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality. The embedded cores can take many forms and generally come from Agere's ASIC libraries. Other offerings allow customers to supply their own core functions for the creation of custom FPSCs.
ORCA Foundry 2000 Development System
The ORCA Foundry 2000 development system is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture, and then place and route it using ORCA Foundry's timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis. The ORCA Foundry 2000 development system interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow: design entry and the bitstream generation stage. Recent improvements in ORCA Foundry allow the user to provide timing requirement information through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Description (continued)
Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A floorplanner is available for layout feedback and control. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation and timing. Timing and simulation output files from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configuration RAM, embedded block RAM, and/or FPSC memory. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, Synopsys Smart Model (R), and complete online documentation. The kit's software couples with ORCA Foundry, providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page of this document.
The architecture consists of four basic elements: programmable logic cells (PLCs), programmable I/O cells (PIOs), embedded block RAMs (EBRs), and systemlevel features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 quadport RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the embedded system bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset.
FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Agere. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. 8
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, singleended, and differential-pair signaling (as shown in Table 1). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels.
Description (continued)
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/flip-flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly tuned networking specific phase-locked loops. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems.
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device, with four PLLs generally provided for FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences. Additional highly tuned and characterized, dedicated phase-locked loops (DPLLs) are included to ease system designs. These DPLLs meet ITU-T G.811 primaryclocking specifications and enable system designers to very tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are targeted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 systems. These DPLLs are not typically included on FPSC devices and are not found on the ORT82G5.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16-, and 32-bit interfaces with optional parity to the Motorola(R) PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 embedded system bus at 66 MHz performance. A system-level microprocessor interface to the FPGA user-defined logic following configuration, through the system bus, including access to the embedded block RAM and general user-logic, is provided by the MPI. The MPI supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes).
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). On-the-fly coefficient modifications are available through the second read/ write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at device configuration time.
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. Master and slave elements are also available for the user-logic and embedded backplane transceiver portion of the ORT82G5. The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for JTAG configuration modes).
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
version II of this device, which will be plug-in compatible to version I, also adds SONET scrambling capability. The version II features are not described in this data sheet. Figure 1 shows the ORT82G5 block diagram. Boundary scan for the ORT82G5 only includes programmable I/Os and does not include any of the embedded block I/Os.
System-Level Features (continued)
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The configuration data can reside externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting insystem programming (ISP) standards (IEEE 1532 Draft).
Backplane Transceiver Interface
The ORT82G5 backplane transceiver FPSC has eight channels, each operating at up to 3.125 Gbits/s (2.5 Gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The CDR macro with 8b/10b provides guaranteed ones density for the CDR, byte alignment, and error detection. The CDR interface provides a physical medium for high-speed asynchronous serial data transfer between system devices. Devices can be on the same PCboard, on separate boards connected across a backplane, or connected by cables. This core is intended for, but not limited to, terminal equipment in SONET/ SDH, Gbit Ethernet, 10 Gbit Ethernet, ATM, fibre-channel, and Infiniband systems. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-speed (up to 3.125 Gbits/s) serial data. Based on data transitions the receiver locks an analog receive PLL for each channel to retime the data, then demultiplexes down to parallel bytes and clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.125 Gbits/s serial data for off-chip communication. The transmitter generates the necessary 3.125 GHz clocks for operation from a lower speed reference clock. This device will support 8b/10b encoding/decoding, which is capable of frame synchronization and physical link monitoring. Figure 2 shows the internal architecture of the ORT82G5 backplane transceiver core.
Additional Information
Contact your local Agere representative for additional information regarding the ORCA Series 4 FPGA devices, or visit our website at: http://www.agere.com/orca
ORT82G5 Overview
Device Layout
The ORT82G5 is a backplane transceiver FPSC with embedded CDR and SERDES circuitry and 8b/10b encoding/decoding. It is intended for high-speed serial backplane data transmission. Built using Series 4 reconfigurable system-on-chips (SoC) architecture, it also contains up to 400k usable FPGA system gates. The ORT82G5 contains an FPGA base array, an eightchannel clock and data recovery macro, and an eightchannel 8b/10b interface on a single monolithic chip.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
ORT82G5 Overview (continued)
8-bit/10-bit DECODER 3.125 Gbits/s TO 1.0 Gbits/s DATA PSUDOSONET FRAMER (VERSION 2) * SCRAMBLING * FIFO ALIGNMENT * SELECTED TOH STANDARD FPGA I/Os
8 FULLDUPLEX SERIAL CHANNELS
CML I/Os
CLOCK/DATA RECOVERY
BYTEWIDE DATA
ORCA SERIES 4 FPGA LOGIC
3.125 Gbits/s TO 1.0 Gbits/s DATA 8-bit/10-bit ENCODER 1023(F)
Figure 1. ORT82G5 Block Diagram
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORT82G5 Overview (continued)
HIGH-SPEED DATA 3.125--2.5--2.0--1.25--1.0 Gbits/s
HIGH-SPEED DATA 3.125--2.5--2.0--1.25--1.0 Gbits/s
SERDES QUAD CHANNEL (WITH 8B/10B ENCODER/DECODER) 1:10
DEMULTIPLEXER
REFERENCE CLOCK
REFERENCE CLOCK
SERDES QUAD CHANNEL (WITH 8B/10B ENCODER/DECODER) 10:1
MULTIPLEXER
10:1
MULTIPLEXER
1:10
DEMULTIPLEXER
QUAD CHANNEL MUX/DEMUX 1:4
DEMULTIPLEXER
QUAD CHANNEL MUX/DEMUX MICROPROCESSOR INTERFACE AND REGISTERS (AUXILIARY BLOCK) 4:1
MULTIPLEXER
4:1
MULTIPLEXER
1:4
DEMULTIPLEXER
MULTI-CHANNEL ALIGNMENT AND FIFO
MULTI-CHANNEL ALIGNMENT AND FIFO
2 TO 1 DATA SELECTOR
2 TO 1 DATA SELECTOR
CLOCK 25--78 MHz
LOW SPEED DATA 25--78 Mbits/s
SYSTEM BUS SIGNALS
LOW SPEED DATA 25--78 Mbits/s
CLOCK 25--78 MHz
FPGA LOGIC AND IOs
DATA AND CONTROL
4K X 36 DUAL PORT RAM
4K X 36 DUAL PORT RAM
2262(F)
Figure 2. Internal High-Level Diagram of ORT82G5 Transceiver
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
ORT82G5 Overview (continued)
The ORT82G5 FPSC combines 8 channels of highspeed full duplex serial links (up to 3.125 Gbits/s) with 400k usable gate FPGA. The major functional blocks in the ASB core are two quad-channel serializer-deserializers (SERDES) including 8b/10b encoder/decoder and dedicated PLLs, XAUI or fibre-channel link-statemachine, 4-to-1 or 1-to-4 MUX/deMUX, multichannel alignment FIFO, microprocessor interface, and 4k x 36 RAM blocks.
MUX/DeMUX Block
The purpose of the MUX/deMUX block is to provide a wide, low-speed interface at the FPGA portion of the ORT82G5 for each channel or data lane. The interface to the SERDES macro runs at 1/10th the bit rate of the data lane. The MUX/deMUX converts the data rate and bit-width so the FPGA core can run at 1/4th this frequency. This implies a range of 25--78 MHz for the data in and out of the FPGA. The MUX/deMUX block in the ORT82G5 is a 4-channel block. It provides an interface between each quad channel SERDES and the FPGA logic.
Serializer and Deserializer (SERDES)
The SERDES block is a quad transceiver for serial data transmission, with a selectable data rate of 1.0-- 1.25 Gbits/s, 2.0--2.5 Gbits/s, or 3.125 Gbits/s. It is designed to operate in Ethernet, fibre channel, Firewire(R), or backplane applications. It features highspeed 8b/10b parallel I/O interfaces, and high-speed CML interfaces. The quad transceiver is controlled and configured with an 8 bit microprocessor interface through the FPGA. Each channel has dedicated registers that are readable and writable. The quad device also contains global registers for control of common circuitry and functions. For complete SERDES description, please refer to the Macrocell Data Sheet, LU6X14FT1.0-1.25/2.0-2.5/ 3.125 Gbits/s Serializer and Deserializer. 8b/10b Encoding/Decoding The ORT82G5 facilitates high-speed serial transfer of data in a variety of applications including Gbit Ethernet, fibre channel, serial backplanes, and proprietary links. The SERDES provides 8b/10b coding/decoding for each channel. The 8b/10b transmission code includes serial encoding/decoding rules, special characters, and error detection. In the receive direction, the user can disable the 8b/10b decoder to receive raw 10 bit words which will be rate reduced by the SERDES. If this mode is chosen, the user must bypass the multichannel alignment FIFOs. In the transmit direction, the 8b/10b encoder must always be enabled (version II will allow it to be disabled). Clocks The SERDES block contains its own dedicated PLLs for transmit and receive clock generation. The user provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data and retime the data with the recovered clock.
Multichannel Alignment FIFOs
The ORT82G5 has a total of 8 channels (4 per SERDES). The incoming data of these channels can be synchronized in several ways, or they can be independent of one other. For example, all four channels in a SERDES can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s. Alternatively, two channels within a SERDES can be aligned together; channel A and B and/or channel C and D. Optionally, the alignment can be extended across SERDES to align all 8 channels. Individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels.
XAUI or Fibre-Channel Link State Machine
Two separate link state machines are included in the ORT82G5. A XAUI compliant link state machine is included in the embedded core to implement the IEEE 802.3ae v2.1 standard. A separate state machine for fibre-channel/Infiband is also provided.
Dual Port RAMs
There are two independent memory blocks in the ASB. Each memory block has a capacity of 4k word by 36 bits. It has one read port, one write port, and four byte-write-enable (active-low) signals. The read data from the memory block is registered so that it works as a pipelined synchronous memory block.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORT82G5 Overview (continued)
FPGA Interface
The FPGA logic will receive/transmit frame-aligned (optional for 8b/10b mode) 32-bit streams of up to 77.8 MHz data (maximum of eight streams in each direction) from/to the embedded core. All frames transmitted to the FPGA can be aligned using comma characters or code violation from each channel, and a single aligned frame pulse is provided to the FPGA logic for each group of aligned channels. For transmit, the generation of a comma or code violation that can be found by the receiving device on the other side of the serial link is created through an independent control signal per channel. If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock and K character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No frame pulses are available in this case and channel alignment cannot be performed.
Backplane Transceiver Core Detailed Description
SERDES
A detailed block diagram of the receive and transmit data paths for a single channel of the SERDES is shown in Figure 3. The transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data are available at the differential CML output terminated in 50 or 75 to drive either an optical transmitter or coaxial media or circuit board/backplane. The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks are asynchronous between channels. The retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the output port. Two-phase receive byte clocks are available synchronous with the parallel words. The receiver also optionally recognizes the comma characters or code violations and aligns the bit stream to the proper word boundary. Bias Section A fractional band-gap voltage generator is included on the design. An external resistor (3.32 k 1%), connected between the pins REXT and VSSREXT generates the bias currents within the chip. This resistor should be able to handle at least 300 A.
FPSC Configuration
Configuration of the ORT82G5 occurs in two stages: FPGA bitstream configuration and embedded core setup. FPGA Configuration Prior to becoming operational, the FPGA goes through a sequence of states, including powerup, initialization, configuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit stream configuration means as discussed in the Series 4 FPGA data sheet. The options for the embedded core are set via registers that are accessed through the FPGA system bus. The system bus can be driven by an external PowerPC compliant microprocessor via the MPI block or via a user master interface in FPGA logic. A simple IP block, that drives the system by using the user register interface and very little FPGA logic, is available in the MPI/System Bus Application Note. This IP block sets up the embedded core via a state machine and allows the ORT82G5 to work in an independent system without an external microprocessor interface.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Reset Operation The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset, or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5 V. Following this event, the device will be ready for normal operation after 3 ms. A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function affects all SERDES channels and resets all microprocessor and internal registers and counters. Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the channel configuration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for normal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES internal registers and counters. The microprocessor registers are not affected. It should also be noted that the embedded block cannot be accessed until after FPGA configuration is complete. Start Up Sequence 1. Initiate a hardware reset by making PASB_RESETN low for 100 ns. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN. During this time configure the FPGA portion of the device. 2. Wait for 100 ns. Configure the following SERDES internal and external registers. Set the following bits in register 30800: -- Bits LCKREFN_[AD:AA] to 1, which implies lock to data. -- Bits ENBYSYNC_[AD:AA] to 1 which enables dynamic alignment to comma. Set the following bits in register 30801: -- Bits LOOPENB_[AD:AA] to 1 if loopback is desired. Set the following bits in register 30900: -- Bits LCKREFN_[BD:BA] to 1 which implies lock to data. -- Bits ENBYSYNC_[BD:BA] to 1 which enables dynamic alignment to comma. Set the following bits in register 30901: -- Bits LOOPENB_[BD:BA] to 1 if loopback is desired. Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132: -- TXHR[0:3] set to 1 if TX half-rate is desired. -- 8B10BT[0:1] set to 1 Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133: -- RXHR[0:3] Set to 1 if RX half-rate is desired. -- 8B10BR[0:3] set to 1. Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30110, 30120, 30130: -- LKI-PLL lock indicator. 1 indicates that PLL has achieved lock. -- SDON-Signal detect output indicator. 0 indicates active data.
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
STBD(A-D) [9:0] 10-BIT REGISTER PARALLEL TO SERIAL PREEMPHASIS HDOUTP_(A,B)(A-D) HDOUTN_(A,B)(A-D)
8B/10B ENCODER
MUX
STBC311 (A-D)
PRBS GENERATOR
TRANSMIT PLL
REFCLKP_(A,B) REFCLKN_(A,B)
SWDSYNC (A-D) SCV (A-D) SRBD(A-D) [9:0] MUX
LINK STATE MACHINE
PRBS CHECKER
HDINP_(A,B)(A-D) 8B/10B DECODER BYTE ALIGNER SERIAL TO PARALLEL RECEIVE PLL HDINN_(A,B)(A-D)
SRBC0 (A-D) SRBC1 (A-D) SBYTSYNC (A-D) ACTIVITY DETECTOR
TO/FROM MUX/DEMUX BLOCK
2263(F)
Figure 3. SERDES Functional Block Diagram for One Channel
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
SERDES Transmit Path (FPGA Backplane)
The transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port from the MUX/deMUX block. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data are available at the differential CML output terminated in 50 or 75 to drive either an optical transmitter, coaxial media, or circuit board/backplane. The STBDx[8:0] (where x is a placeholder for one of the letters, A--D) ports carry unencoded character data in this design. The time-division multiplexer in the ORT82G5 is only 9 bits wide. The 10th bit (STBDx[9]) of each data lane into the SERDES is held constant. It is not possible to use the ORT82G5 for normal data communication without enabling SERDES 8b/10b encoding. The functional mode uses the STBCx311 SERDES output as the reference clock. The frequency of this clock will depend on the half-rate/full-rate control bit in the SERDES; and the frequency of the REFCLK ports and/or that of the high-speed serial data. The SERDES TBCKSEL control bit must be configured to a 0 for each channel in order for this clocking strategy to work. A falling edge on the STBC311x clock port will cause a new data character to be sent from STBDx[9:0] to the SERDES block with a latency of 5 STBC311x clock cycles at the high-speed serial output.
HDOUTPx, HDOUTNx TRANSMIT DATA 1.0--3.125 Gbits/s 100--156 MHz REFERENCE CLOCK DATA BYTE STBDx[7:0] K-CONTROL STBDx{8] GROUND STBDx[9] (X 9) PLL STBC311x MUX/DEMUX BLOCK EMBEDDED CORE 4:1 MULTIPLEXER
10 10:1 MULTIPLEXER 8B/10B ENCODER
9
8
SERDES BLOCK
STBDx[9:0]
p
q
r
s
t
x
y
z

STBC311x
LATENCY = 5 STBC311x CLOCKS HDOUTx
pppp pppppp 0123 456789
2264(F)
Figure 4. ORT82G5 Transmit Path for a Single SERDES Channel
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
Transmit Preemphasis and Amplitude Control
The transmitter's CML output buffer is terminated on-chip to optimize the data eye as well as to reduce the number of discrete components required. The differential output swing reaches a maximum of 1.2 VPP in the normal amplitude mode. A half amplitude mode can be selected via configuration register bit HAMP Half amplitude mode can . be used to reduce power dissipation when the transmission medium has minimal attenuation. A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maximize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables. The degree of preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in Table 2. The high-pass transfer function of the preemphasis circuit is shown below, where the value of a is shown in Table 2. H(z) = (1 - az -1) Table 2. Preemphasis Settings PE1 0 0 1 1 PE0 0 1 0 1 Amount of Preemphasis (a) 0% (No Preemphasis) 12.5% 12.5% 25%
SERDES Receive Path (Backplane FPGA)
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks are asynchronous between channels. The retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the output port. Two-phase receive byte clocks are available synchronous with the parallel words. The receiver also recognizes the comma characters and aligns the bit stream to the proper word boundary. The receive PLL has two modes of operation as follows: lock to reference and lock to data with retiming. When no data or invalid data is present on the HDINP and HDINN pins, the receive VCO will not lock to data and its frequency can drift outside of the nominal 100 ppm range. Under this condition, the receive PLL will lock to REFCLK for a fixed time interval and then will attempt to lock to receive data. The process of attempting to lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per channel to force the receive PLL to always lock to the reference clock. The activity detector monitors the presence of data on each of the differential high-speed input pins. In the absence of amplitude qualified data on the inputs the chip automatically goes into sleep mode. This function can, however, be disabled through the control interface. The PRBS checker is a built-in bit error rate tester (BERT). When enabled, it produces a one-bit PRBSCHK output to indicate whether there was an error in the loopback data.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Data from a SERDES channel appears in 10-bit raw form or 8-bit decoded form at the SRBDx[9:0] port (where x is a placeholder for one of the letters, A-D) with a latency of approximately 14 cycles. Accompanying this data are the comma-character indicator (SBYTSYNCx), clocks (SRBC0x, and SRBC1x), link-state indicator (SWDSYNCx), and code-violation indicator (SCVx). With the 8B10BR control bit of the SERDES channel set to 1, the data presented at SRBDx[9:0] will be decoded characters. Bit 8 will indicate whether SRBDx[7:0] represents an ordinary data character (bit 8 == 0), or whether SRBDx[7:0] represents a special character, like a comma. When 8B10BR is set to 0, the data at SRBDx[9:0] will be encoded characters. The XAUI link-state machine should not be used in this mode of operation. When in XAUI mode, the MUX/deMUX looks for /A/ (as defined in IEEE 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work.
DATA 40
SCVx
MULTIPLEXER
LINK STATE MACHINE
8B/10B ENCODER
MULTI-CHANNEL ALIGNMENT
HDINPx, HDINNx RECEIVE DATA 1.0--3.125 Gbits/s 100--156 MHz REFERENCE CLOCK
CODE GROUP ALIGNMENT
XAUI LINK STATE MACHINE
2:1 MULTIPLEXER (X 40)
10:1
SRBDx[9:0] SBYTSYNCx SWDSYNCx SRBC0x
1:4 DEMULTIPLEXER (X 10)
32 DATA 4 K_CTRL COMMADET 25--78 MHZ CLOCK
36 FIFO
DATA
PLL & CDR
SRBC1x MUX/DEMUX BLOCK EMBEDDED CORE
SERDES BLOCK
CHANNEL ALIGN BLOCK
1-bit HDINx pppp pppppp q 0123 456789 0

r
rrrrrrrsssss 2345678901234
LATENCY = APPROX 23 CLOCKS SRBDx[9:0] p
10-bit SRBDx[9:0] SRBC0x
p
q
r
s
t
x
y
z

2265(F)
SRBC1x SBYTSYNCx, SVCx SWDSYNCx
Figure 5. ORT82G5 Receive Path for a Single SERDES Channel 20 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Table 4 shows the relationship between the data rates, the reference clock, and the RWCKx clocks. For more information on the reference clock input requirements and connections to either single ended or differential inputs, see the LU6X14FT SERDES Macrocell Data sheet or the associated reference clock application note. Table 3. Transmit PLL Clock and Data Rates Data Rate 1.0 Gbits/s 1.25 Gbits/s 2.0 Gbits/s 2.5 Gbits/s 3.125 Gbits/s Reference Clock 100 MHz 125 MHz 100 MHz 125 MHz 156 MHz TCK78[A, B] Clock 25 MHz 31.25 MHz 50 MHz 62.5 MHz 78 MHz Rate Half Half Full Full Full
Backplane Transceiver Core Detailed Description (continued)
8b/10b Encoding/Decoding
The 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format according to the IEEE 802.3z standard. Input pins SRBDx<7:0> (where x is a placeholder for one of the letters, A--D) are used for 8 bit unencoded data and SRBDx<8> is used as the K_control input to indicate whether the 8 data bits need to be encoded as special characters (K_control = 1) or as data characters (K_control = 0). When the encoder is bypassed SRBDx<9:0>serve as the data bits for the 10-bit encoded data. Within the definition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission characters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to SRBDx[0], bit b to SRBDx[1], bit c to SRBDx[2], bit d to SRBDx[3], bit e to SRBDx[4], bit i to SRBDx[5], bit f to SRBDx[6], bit g to SRBDx[7], bit h to SRBDx[8], and bit j to SRBDx[9]. The data SRBDx[9:0] is transmitted serially with SRBDx[0] transmitted first and SRBDx[9] transmitted last. For an 8-bit unencoded data, the 8-bit unencoded data SRDBx[7:0] is represented as HGF EDCBA SRDBx[8] represents the K_CTRL bit and SRDBx[9] is unused (tied to logic 0). SRBDx[0] is still transmitted first and SRBDx[9] transmitted last.
Note: The selection of full-rate or half-rate for a given reference clock speed is set by a bit in the transmit control register and can be set per channel.
Table 4. Receive PLL Clock and Data Rates Data Rate 1.0 Gbits/s 1.25 Gbits/s 2.0 Gbits/s 2.5 Gbits/s 3.125 Gbits/s Reference Clock 100 MHz 125 MHz 100 MHz 125 MHz 156 MHz RWCKx Clocks 25 MHz 31.25 MHz 50 MHz 62.5 MHz 78 MHz Rate Half Half Full Full Full
SERDES Transmit and Receive PLLs
The high-speed transmit and receive serial data can operate at 1.0--1.25 Gbits/s or 2.0--3.125 Gbits/s depending on the state of the control bits from the microprocessor interface. Table 3 shows the relationship between the data rates, the reference clock, and the transmit TWCKx clocks. The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks are asynchronous between channels. The retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the output port. RWCKx receive byte clocks are available synchronous with the parallel words. The receiver also recognizes the comma characters and aligns the bit stream to the proper word boundary.
Note: The selection of full-rate or half-rate for a given reference clock speed is set by a bit in the receive control register and can be set per channel.
Reference Clock
The differential reference clock is distributed to all four channels. Each channel has a differential buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jitter components in the dc--5 MHz range should be minimized. Note: The reference clock, REFCLK, is equivalent to REFINP and REFINN; throughout the text simply refer to the reference clock as REFCLK.
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Byte Alignment
When ENBYSYNC = 1, the ORT82G5 recognizes the comma sequence and aligns the 10-bit comma containing character to the word boundary. BYTSYNC = 1 when the parallel output word contains a byte-aligned comma containing character. The BYTSYNC flag will continue to pulse a logic 1 whenever a byte aligned comma containing character is at the parallel output port.
WDSYNC = 0. While in this state, the machine looks for a particular number of consecutive idle ordered sets without any invalid data transmission in between before declaring synchronization achieved. Synchronization achieved is indicated by asserting WDSYNC = 1. Specifically, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running disparity based code violation in between. In the event of any such code violation, the machine would reset itself to the ground state and start its search for the idle ordered sets again. In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS is indicated by the status of WDSYNC output which now transitions from 1 to 0. At this point the machine attempts to establish the link yet again. Figure 6 shows the state diagram for the fibre-channel link state machine.
Link State Machines
Two link state machines are included in the ORT82G5, one for XAUI applications and a second for fibre-channel applications. The fibre-channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. The machine wakes up in the loss of synchronization state upon powerup reset. This is indicated by
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1) VW CV a 2 VW OS CV h LOSS OF SYNCHRONIZATION (WDSYNC = 0) OS CV g CV b 2 VW VW CV c 2 VW VW CV d VW
OS LOS = 1 f
LSM_ENABLE
e OS
RST
+
POWERUP RESET
OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER) VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
2266(F)
Figure 6. Fibre-Channel Link State Machine State Diagram 22 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
XAUI Link Synchronization Function
For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma character such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that cannot appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful for delimiting code-groups in a serial stream.This mechanism incorporates a hysteresis to prevent false synchronization and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled until the lane achieves synchronization. The synchronization state diagram is shown in Figure 1. Table 1 and Table 2 describe the state variables used in Figure 1. Table 5. XAUI Link Synchronization State Diagram Notation--Variables Variable sync_status Description FAIL: Lane is not synchronized (correct 10-bit alignment has not been established). OK: Lane is synchronized. OK_NOC: Lane is synchronized but a comma character has not been detected in the past TBD seconds. TRUE: Align subsequent 10-bit words to the boundary indicated by the next received comma. FALSE: Maintain current 10-bit alignment. Current number of consecutive cg_good indications.
enable_CDET
gd_cg
Table 6. XAUI Link Synchronization State Diagram--Functions Function sync_complete cg_comma cg_good cg_bad no_comma Description Indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. Indication that a valid code-group, with correct running disparity, containing a comma has been received. Indication that a valid code-group with the correct running disparity has been received. Indication that an invalid code-group has been received. Indication that comma timer has expired. The timer is initialized upon receipt of a comma.
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
reset
Loss_of_Sync sync_status <= FAIL enable_CDET <= TRUE sync_complete Comma_Detect_1 enable_CDET <= FALSE cg_bad cg_comma Comma_Detect_2
cg_bad
cg_comma Comma_Detect_3
cg_bad cg_comma
Sync_Aqc'd_1 sync_status <= OK no_comma cg_bad Sync_Aqc'd_2 gd_cg <= 0 cg_good cg_bad Sync_Aqc'd_3 gd_cg <= 0 cg_good cg_bad Sync_Aqc'd_4 gd_cg <= 0 cg_good cg_bad cg_good*(gd_cg=3) cg_good*(gd_cg=3)
Sync_Aqc'd_1a sync_status <= OK_NOC cg_bad cg_comma Sync_Aqc'd_2a gd_cg <= gd_cg+1 cg_bad cg_good*(gd_cg=3) Sync_Aqc'd_3a gd_cg <= gd_cg+1 cg_bad Sync_Aqc'd_4a gd_cg <= gd_cg+1 cg_bad cg_good* (gd_cg != 3) cg_good* (gd_cg != 3) cg_good* (gd_cg != 3)
2273(F)
Figure 7. XAUI Link Synchronization State Diagram
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
values. The data bytes are conveyed to the MUX via the TWDx[31:0] ports. The control bits are TCOMMAx[3:0]. The clock is TSYS_CLK(A, B). Both the data and control are strobed into the MUX at this interface on the rising edge of TSYS_CLK(A, B). Besides taking in a clock for capture, the interface sends back a clock of the same frequency, but arbitrary phase. This clock, TCK78, is derived from one of the 4 channels of MUX. Within each MUX is a divide-by-4 of the SERDES TBCx311 clock used in synchronizing the transmit data words to the TBCx311 clock domain. TCKSEL[1:0] bits select the source channel of TCK78. When TCKSEL[1:0] is 00, the clock source is channel A, 01 is channel B, 10 is channel C, and 11 is channel D. In many cases, this TCK78 clock is used to drive the low-speed clock in the FPGA that is connected to the TSYS_CLK(A, B) signal.
Backplane Transceiver Core Detailed Description (continued)
MUX/DeMUX Block
Transmit Path (FPGA Backplane) The MUX is responsible for taking 36 bits of data/control at the low-speed transmit interface and up-converting it to 9 bits of data/control at the SERDES transmit interface. The MUX has 2 clock domains: one based on a clock received from the SERDES; the other that comes from the FPGA at 1/4 the frequency of the SERDES clock. The time sequence of interleaving data/control values is shown in Figure 8 below. The low-speed transmit interface consists of a clock, 4 data byte values and a control bit for each of the byte
SERDES BLOCK 10 8B/10B ENCODER 9 8
DATA BYTE STBDx[7:0] K-CONTROL STBDx[8] PARALLEL TO SERIAL (X 9) DIVIDE BY 4
MUX BLOCK 32 FIFO 4 TWDx[31:0] TCOMMAx[3:0] TSYS_CLK(A, B)
GROUND STBDx[9] PLL STBC311x
4 CHANNELS
MUX
TCK78(A,B)
EMBEDDED CORE 40-bit TWDx[31:0] p q r s 7-0 7-0 7-0 7-0 t x y z 7-0 7-0 7-0 7-0
TCKSEL[1:0]
FPGA
TCOMMAx[3:0]
p 8
q 8
r
8
s 8
t
8
x 8
y 8
z 8
LATENCY = 4 TSYS_CLK (A, B) CLOCKS
10-bit (THE MSB ALWAYS TIED TO LOGIC 0) p q r s t x y z
STBDx[9:0]
TSYS_CLK (A, B)
2267(F)
Figure 8. Transmit MUX Block for a Single SERDES Channel Agere Systems Inc. 25
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Receive Path (Backplane FPGA) The deMUX has to accumulate four sets of characters presented to it at the SERDES receive interface and put these out at one time at the low-speed receive interface. Another task of the deMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. This feature will be referred to as word alignment in other areas of this document. Word alignment will only occur when the communication channel is synchronized. When there is no synchronization of the link, the deMUX will continue to output 4-byte words at some arbitrary, but constant, boundary.
The deMUX passes on to the channel alignment FIFO block a set of control signals that indicate the location of the synchronizing event. RCOMMAx[3:0] are these indicators. If there is no link synchronization, all of the RCOMMAx[3:0] bits will be 0s independent of synchronizing events that come in. When the link is synchronized, then the bit that corresponds to the time of the synchronization event will be set to a 1. The relationship between a time sequence of values input at SRBDx[7:0] to the values output at RWDx[31:0] is shown in Figure 9 below. A parallel relationship exists between SRBDx[8] and RWBIT8x[3:0] as well as between SRBDx[9] and RWBIT9x[3:0].
SCVx 8B/10B ENCODER
XAUI LINK STATE MACHINE
RWBIT9x[3:0] RWBIT8x[3:0]
p 9 p 8 p
q 9 q 8
r
9 8
s 9 s 8
t
9 8
x 9 x 8
y 9 y 8
z 9 z 8
SRBDx[9:0] SBYTSYNCx SWDSYNCx SRBC0x 1:4 DEMUX (X 10)
r
t t
RWDx[31:0] RCOMMAx[3:0] RWCKx
q r s 7-0 7-0 7-0 7-0 q c r c s c
x y z 7-0 7-0 7-0 7-0 t c x c y c z c
PLL & CDR
SRBC1x
p c
SERDES BLOCK
DEMUX BLOCK
10-bit SRBDx[7:0] p q r s t x y z 40-bit p q t x
LATENCY = 4 RWCKx CLOCKS RWDx[31:24] RWDx[23:16]
RWDx[15:8] RWDx[7:0]
r s
y z
2268(F)
Figure 9. Receive DeMUX Block for a Single SERDES Channel
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Alternatively, two channels within a SERDES can be aligned together; channel A and B and/or channel C and D can form a pair as shown in Figure 13.
Backplane Transceiver Core Detailed Description (continued)
SERDES A STREAM A SERDES A STREAM B SERDES A SERDES A STREAM C SERDES A STREAM D FIFO SYNC SERDES B STREAM A SERDES B STREAM B SERDES B SERDES B STREAM C SERDES B STREAM D
ALL 4 ALIGNMENT OF SERDES A AND SERDES B
SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES B Stream C SERDES B Stream D SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES B Stream C SERDES B Stream D
t1 t0
0673(F)
Figure 11. Example of SERDES A Alignment and SERDES B Alignment
ALL 8 ALIGNMENT OF SERDES A AND SERDES B
SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES B Stream C SERDES B Stream D
5-8577 (F)
SERDES B Stream C SERDES B Stream D
Figure 10. Interconnect of Streams for FIFO Alignment
t0
0674
Multichannel Alignment (Backplane FPGA)
The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block (Figure 10) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures that matching SERDES streams will arrive at the FPGA end in perfect data sync. The ORT82G5 has a total of 8 channels (4 per SERDES). The incoming data of these channels can be synchronized in several ways, or they can be independent of one other. For example, all four channels in a SERDES can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s as shown in Figure 11. Optionally, the alignment can be extended across SERDES to align all 8 channels in ORT82G5 as shown in Figure 12. Individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels. Agere Systems Inc.
Figure 12. Example of SERDES A and B Alignment
TWO CHANNEL ALIGNMENT
SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES B Stream C SERDES B Stream D SERDES A Stream A SERDES A Stream B SERDES A Stream C SERDES A Stream D SERDES B Stream A SERDES B Stream B SERDES B Stream C SERDES B Stream D
t0 t1 t2 TWIN ALIGNMENT OF STREAM A & B OF SERDES A TWIN ALIGNMENT OF STREAM C & D OF SERDES A TWIN ALIGNMENT OF STREAM C & D OF SERDES B
0675
Figure 13. Example of Multiple Twin Channel Alignment 27
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
The multiplexed, receive word outputs to the FPGA are shown in Figure 14. These are each 40 bits wide. There are eight of these interfaces, one for each data lane. Each consist of four 10-bit characters, or four decoded characters (each 8 bits + 1 bit K_CTRL) + CH248_SYNCx status indicator bit depending on setting of NOCHALGNx control register bits. Note that there is one control bit for a bank of channels, for a total of two control bits. Also, note that while 10 bits are provided for each character when NOCHALGNx = 1, only the lower 9 bits of each character will be meaningful if the 8B10BR bit is configured to 1 for that SERDES channel. With x representing the bank (placeholder for A or B) and y representing the channel (placeholder for A, B, C, or D) the 40-bit MRWDxy[39:0] is allocated as in Table x. In the receive path, each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels. The input to the FIFO consists of 36-bit demultiplexed data, RWBYTESYNC[3:0], RWDx[31:0], and RWBIT8x[3:0]. The four RWBYTESYNC bits are control signals, e.g., they can be the COMMADET signals indicating the presence of COMMA character. The other 32 RWD bits are the 4 characters from the 8b/10b decoder. The RWBIT8 indicates the presence of Km.n control character in the receive data byte. Only RWBIT8 and RWD inputs are stored in the FIFO. During alignment process, RWBYTESYNC is used to synchronize multiple channels. If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will set the FIFO-readaddress to the middle of the FIFO, at the first assertion of RWBYTESYNC after reset or after the resync command.
40
2:1 MULTIPLEXER (X 40)
MRWDx 40
XAUI LINK STATE MACHINE 36 MULTI-CHANNEL ALIGNMENT
1:4
DEMUX
RWDx[31:0] RWBYTESYNC[3:0]
FIFO RSYS_CLK(A,B)
(FROM GLOBAL OR SECONDARY FPGA
(X 10) RWCKx DEMUX
CLOCK NETWORKS) CHANNEL ALIGN RWCKx
(TO LOCAL FPGA SECONDARY CLOCK NETWORK) (TO GLOBAL FPGA SYSTEM CLOCK NETWORK)
4 CHANNELS
MUX
RCK78(A,B)
RCKSEL[1:0] EMBEDDED CORE FPGA
2269(F)
Figure 14. Multichannel Alignment FIFO Block for a Single SERDES Channel
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
the write and the read pointer of the FIFO) set the following bit to zero, and then set it to 1.
s
Backplane Transceiver Core Detailed Description (continued)
The use of the FIFO is controlled by configuration bits, and the raw demultiplexed data can also be sent to the FPGA directly, by passing the alignment FIFO. The control register bits for alignment FIFO in ORT82G5 are described below. Table 7. Multichannel Alignment Modes Register Bits FMPU_SYNMODE_xx 00 01 10 11 Mode No multichannel alignment. Twin channel alignment. Quad channel alignment. Eight channel alignment.
FMPU_RESYNC1_xx where xx is one of A[A:D] and B[A:D]
A two-to-one multiplexor is used to select between aligned or nonaligned data to be sent to the FPGA on MRWDxy[39:0]. With x representing the bank (placeholder for A or B) and y representing the channel (placeholder for A, B, C or D), the 40-bit MRWDxy[39:0] is allocated as shown in Table 8.
Alignment Sequence
1. Follow steps 1 and 2 in the start up sequence described previously. 2. Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that, any changes to the SERDES configuration bits should be followed by a software reset. 3. Wait for 3 ms. REFCLK_[P N] should be toggling , by this time. During this time, configure the following registers. Set the following bits in registers 30820, 30920
s
where xx is one of A[A:D] and B[A:D]. To align all eight channels:
s s
FMPU_SYNMODE_A[A:D] = 11 FMPU_SYNMODE_B[A:D] = 11 FMPU_SYNMODE_A[A:D] = 10 FMPU_SYNMODE_A[A:B] = 01 for channel AA and AB FMPU_SYNMODE_A[C:D] = 01 for channel AC and AD
To align all four channels in SERDES A:
s
To align two channels in SERDES A:
s
XAUI_MODEx-set to 1 for XAUI mode or keep the default value of 0.
Enable channel alignment by setting sync bits in registers 30811, 30911
s
s
FMPU_SYNMODE_xx. Set to appropriate values for 2, 4, or 8 alignment.
Similar alignment can be defined for SERDES B. To enable/disable synchronization signal of individual channel within a multi-channel alignment group:
s s
Set RCLKSELx and TCKSELx bits in registers 30A00.
s
FMPU_STR_EN_xx = 1 enabled FMPU_STR_EN_xx = 0 disabled where xx is one of A[A:D] and B[A:D].
s
RCKSELx-choose clock source for 78 MHz RCK78x. TCKSELx-Choose clock source for 78 MHz TCK78x.
To re-synchronize a multi-channel alignment group set the following bit to zero, and then set it to 1.
s
4. Send data on serial links. Monitor the following status/alarm bits: Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130.
s
FMPU_RESYNC8 for eight channel A[A:D] and B[A:D] FMPU_RESYNC4A for quad channel A[A:D] FMPU_RESYNC2A1 for twin channel A[A:B] FMPU_RESYNC2A2 for twin channel A[C:D] FMPU_RESYNC4B for quad channel B[A:D] FMPU_RESYNC2B1 for twin channel B[A:B] FMPU_RESYNC2B2 for twin channel B[C:D]
s s s s s s
LKI-PLL lock indicator. A 1 indicates that PLL has achieved lock. SDON-signal detect output indicator. A 0 indicates active data.
s
Monitor the following status bits in registers 30804, 30904
s
To resynchronize an independent channel (resetting Agere Systems Inc.
XAUISTAT_xx-In XAUI mode, they should be 01 or 10. 29
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Monitor the following status bits in registers 30805, 30905
s s
DEMUXWAS_xx-They should be 1 indicating word alignment is achieved. CH248_SYNCxx-They should be 1 indicating channel alignment. this is cleared by resync.
5. Write a 1 to the appropriate resync registers 30820, 30920. Note that this assumes that the previous value of the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. Check out-of-sync and FIFO overflow status in registers 30814 (Bank A).
s s
SYNC4_A_OOS, SYNC4_A_OVFL-by 4 alignment. SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A!_OOS, SYNC2_A!_OVFL-by 2 alignment.
Check out-of-sync status in registers 30914 (Bank 4).
s s
SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment. SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment.
Check out-of-sync status in register 30A03
s
SYNC8_OOS, SYNC8_OVFL-by 8 alignment.
If out-of-sync bit is 1 or FIFO overflow is 1 then rewrite a 1 to the appropriate resync registers and monitor the OOS and OVFL bits again. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from a second alignment FIFO until all channels requesting alignment on the current device AND all channels requesting alignment on the other device are aligned (as indicated on the K_CTRL character). This second alignment FIFO will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for both devices be driven by the same signal. XAUI Lane Alignment Function (Lane Deskew) In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column. Figure 2 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that at least 80 bits of skew compensation capability should be provided, which the ORT82G5 significantly exceeds.
LANE 0 K R R K K R R R R K K K R R R A K K R R R A K K K R R K A K K R R K A K K R R R K K K R R R K K K R R R K K R R K R K
LANE 1 LANE 2 K
LANE 3
LANE 0 LANE 1 LANE 2 LANE 3
K K K K
R R R R
R R R R
K K K K
R R R R
K K K K
A A A A
R R R R
K K K K
K K K K
R R R R
K K K K
R R R R
R R R R
K K K K
2392(F)
Figure 15. De-Skew Lanes by Aligning /A/ Columns 30 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
Table 8. Definition of Bits of MRWDxy[39:0] Bit Index 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NOCHALGNx = 1 b9 of char 1 b8 of char 1 b7 of char 1 b6 of char 1 b5 of char 1 b4 of char 1 b3 of char 1 b2 of char 1 b1 of char 1 b0 of char 1 b9 of char 2 b8 of char 2 b7 of char 2 b6 of char 2 b5 of char 2 b4 of char 2 b3 of char 2 b2 of char 2 b1 of char 2 b0 of char 2 b9 of char 3 b8 of char 3 b7 of char 3 b6 of char 3 b5 of char 3 b4 of char 3 b3 of char 3 b2 of char 3 b1 of char 3 b0 of char 3 b9 of char 4 b8 of char 4 b7 of char 4 b6 of char 4 b5 of char 4 b4 of char 4 b3 of char 4 b2 of char 4 b1 of char 4 b0 of char 4 NOCHALGNx = 0 CH248_SYNCx K_CTRL for char 1 b7 of char 1 b6 of char 1 b5 of char 1 b4 of char 1 b3 of char 1 b2 of char 1 b1 of char 1 b0 of char 1 n/c K_CTRL for char 2 b7 of char 2 b6 of char 2 b5 of char 2 b4 of char 2 b3 of char 2 b2 of char 2 b1 of char 2 b0 of char 2 n/c K_CTRL for char 3 b7 of char 3 b6 of char 3 b5 of char 3 b4 of char 3 b3 of char 3 b2 of char 3 b1 of char 3 b0 of char 3 n/c K_CTRL for char 4 b7 of char 4 b6 of char 4 b5 of char 4 b4 of char 4 b3 of char 4 b2 of char 4 b1 of char 4 b0 of char 4
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Loopback Modes
The device can be exercised in four possible loopback modes. These loopback modes are identified as:
s s s s
High-speed serial loopback Parallel loopback at the SERDES boundary Parallel loopback at MUX/deMUX boundary excluding SERDES Operational mode full loopback using the PRBS generator/checker
These four loopback modes are described next.
High-Speed Serial Loopback
The high-speed serial loopback involves the transmit signal at the serial interface being looped back internally to the receive circuitry. The serial loopback path does not include the high-speed input and output buffers. The HDOUTP HDOUTN outputs are active in this loopback mode, but the CML input buffers are powered down. The , data are sourced at the LDIN[9:0] pins and detected at the LDOUT[9:0] pins. The device is otherwise in its normal mode of operation. The data rate selection bits, TXHR and RXHR, in the channel configuration registers must be configured to carry the same value and the PRBS Generator and Checker are excluded by setting the PRBS configuration bit to 0. The 8b/10b encoder/decoder can optionally be configured into or out of the loopback path. The following Table 9 illustrates the control interface register configuration for the high-speed serial loopback. Table 9. High-Speed Serial Loopback Configuration Register Address 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 30005, 30105 30006, 30106 Bit Value Bit 0 = 0 or 1 Bit Name TXHR Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value. Set to 0.
Bit 7 = 0 or 1
8B10BT
Bit 0 = 0 or 1
RXHR
Bit 3 = 0 or 1
8B10BR
Bit 0 = 0
PRBS
Bit 7 = 1
TESTEN
Bit 7 = 1 Bits[4:0] = 00000
GTESTEN --
Set to 1 if the loopback is done on a per-channel basis. However, if the loopback is done globally on all the four channels, this bit can be set to 0 but bit 7 of register 5 must be set to 1. Set to 1 if the loopback is done globally on all four channels. Set to 00000.
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Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
Parallel Loopback at the SERDES Boundary
The parallel loopback involves the parallel buses LDIN[9:0] and LDOUT[9:0]. The loopback connection is made such that LDIN[9:0] is logically equivalent to LDOUT[9:0]. In the parallel loopback mode, the LDOUT[9:0] pins remain active. The receive data are sourced at the HDINP HDINN pins and detected at the HDOUTP HDOUTN , , pins. The device is otherwise in its normal mode of operation. The data rate selection bits TXHR and RXHR in the channel configuration registers must be configured to carry the same value and the PRBS generator and checker are excluded by setting the PRBS configuration bit to 0. Also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bT and 8b10bR configuration bits to 0. Table 10 illustrates the control interface register configuration for the parallel loopback. Table 10. Parallel Loopback Configuration Register Address 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 Bit Name TXHR 8B10BT Comments Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0. The 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. Set to 0 or 1. TXHR and RXHR bits must be set to the same value. Set to 0. The 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to 0. Set to 0. Set to 1 if the loopback is done on a per-channel basis. However, if the loopback is done globally on all the four channels, this bit can be set to 0 but bit 7 of register 5 must be set to 1. Set to 1 if the loopback is done globally on all four channels. Set to 00001.
Bit 0 = 0 or 1 Bit 3 = 0
RXHR 8B10BR
Bit 0 = 0 Bit 7 = 1
PRBS --
30005, 30105 30006, 30106
Bit 7 = 1 Bits[4:0] =00001
-- --
Parallel Loopback at MUX/DeMUX Boundary Excluding SERDES
This is a low-frequency testmode. This parallel loopback involves the parallel buses SRBDx[9:0] and STBDx[9:0]. The loopback connection is made such that SRBDx[9:0] is logically equivalent to STBDx[9:0] and STBDx[9:0] remains active, thus bypassing the SERDES. Data can be sent from the FPGA through TWDxx signals and monitored on MRWDxx signals. This test is enabled by setting the pin PLOOP_TEST_ENN to 1. PASB_TESTCLK must be running in this mode at 4x frequency of RSYS_CLK[A, B] or TSYS_CLK[A, B].
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Backplane Transceiver Core Detailed Description (continued)
Operational Mode Full Loopback Test Using The PRBS Generator/Checker The operational mode full loopback test forms one of the normal operational modes of the device. The loopback can be either internal to the device or external to it. To perform the test with internal loopback, the LOOPENB pin should be set to a logic 1. The test includes the PRBS generator in the transmit path and the PRBS checker in the receive path. In this case, the device is placed in its normal operational mode with all the functional blocks in the transmit and the receive path active. The transmit data is generated by an LFSR. The generated word is then serialized and looped back (either internally or externally) to the receiver. The receiver first deserializes the 8-bit word to regenerate the transmitted 8-bit word. The PRBS checker on the receiver compares the regenerated 8-bit word against the transmitted 8-bit word on a word by word basis and signals a mismatch by asserting a PRBSCHK alarm status bit. During this test, the receiver regenerated 8-bit words can also be observed on the device output ports. The PRBS checker contains a watchdog timer which asserts the time-out alarm status bit, PRBSTOUT, if the PRBS test cannot progress beyond its start state within a reasonable time interval. This time interval is set by the precision of the watchdog timer. Both the PRBSCHK and the PRBSTOUT alarms can generate an interrupt if their corresponding masks are disabled.
ASB Memory Blocks
This section describes the memory blocks in the embedded core. Note that although the memory blocks are in the embedded core part of the chip, they do not interact with the rest of the embedded core circuits. They are standalone blocks designed specifically to increase RAM capacity in the ORT82G5 chip, and will be used by the soft IP cores in the FPGA. There are two independent memory blocks in the embedded core. These are in addition to the block RAMs found in the FPGA portion of the ORT82G5. A block diagram of a memory block is shown in Figure 16. Each memory block has a capacity of 4K word by 36 bit. It has one read port and one write port and four byte-write-enable (active-low) signals. The read data from the memory block is registered so that it works as a pipelined synchronous memory block. A block diagram of the memory block in shown below in Figure 16.The minimum timing specifications are shown in Figure 18.
D_x[35:0] CKW_x CSWA_x CSWB_x AW_x[10:0] BYTEWN_x[3] BYTEWN_x[2] BW[34,23:16] BYTEWN_x[1] BW[33,15:8] BYTEWN_x[0] BW[32,7:0] WRITE PORTS BW[35,31:24]
4K x 36 MEMORY BLOCK (1 OF 2)
READ PORTS CKR_x Q_x[35:0] CSR_x AR_x[10:0]
2270(F)
Figure 16. Block Diagram of Memory Block 34 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Backplane Transceiver Core Detailed Description (continued)
1.5 ns CKW 0.5 ns CSW[A,B] 0.3 ns
2.0 ns
0.5 ns AW[10:0] 0.5 ns D[35:0] 0.7 ns BYTEWN[3:0]
0.3 ns
0.3 ns
0.3 ns
2271(F)
Figure 17. Minimum Timing Specs for Memory Blocks-Write Cycle
1.5 ns CKR 4.5 ns AR[10:0], CSR 0.5 ns Q[35:0] 0 ns
1.5 ns
2.0 ns
2272(F)
Figure 18. Minimum Timing Specs for Memory Blocks-Read Cycle
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map
Definition of Register Types
The registers in ORT82G5 are 8-bit memory locations, which in general can be classified into the following types: Status Register and Control Register. Status Register Read-only register to convey the status information of various operations within the FPSC core. An example is the state of the XAUI link-state-machine. Control Register Read-write register to set up the control inputs that define the operation of the FPSC core. The SERDES block within the ORT82G5 core has a set of status and control registers for it's operation. The detailed description of them can be found in the SERDES data sheet. There is another group of status and control registers which are implemented outside the SERDES, which are related to the SERDES and other functional blocks in the FPSC core. They will be described in detail here. Each SERDES has four independent channels, which are named A, B, C, or D. Using this nomenclature, the SERDES A channels are named as AA, AB, AC, and AD, while SERDES B channels will be BA, BB, BC, and BD. Table 11. Structural Register Elements
Address (Hex) Description
300xx 301xx 308xx 309xx 30A0x
SERDES A, internal registers. SERDES B, internal registers. Channel A [A:D] registers (external to SERDES blocks). Channel B [A:D] registers (external to SERDES blocks). Global registers (external to SERDES blocks).
A full memory map is included in Table 12.
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Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12 details the memory map for the ASIC core of the ORT82G5 device. This table shows the databus oriented for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the user master interface is used to preform operations to the ASIC core then the databus must be used in the opposite notation, where DB7 is the MSB and DB0 is the LSB. Table 12. Memory Map
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Alarm Registers (Read Only) 30000 SDON_AA Receive Signal Detect Output, Bank A, Channel A. When SDON_AA = 0, then active data is present. SDON_AB Receive Signal Detect Output, Bank A, Channel B. When SDON_AB = 0, then active data is present. SDON_AC Receive Signal Detect Output, Bank A, Channel C. When SDON_AC = 0, then active data is present. SDON_AD Receive Signal Detect Output, Bank A, Channel D. When SDON_AD = 0, then active data is present. LKI_AA Receive PLL Lock Indication, Bank A, Channel A. When LKI_AA = 1, then PLL receive is locked. LKI_AB Receive PLL Lock Indication, Bank A, Channel B. When LKI_AB = 1, then PLL receive is locked. LKI_AC Receive PLL Lock Indication, Bank A, Channel C. When LKI_AC = 1, then PLL receive is locked. LKI_AD Receive PLL Lock Indication, Bank A, Channel D. When LKI_AD = 1, then PLL receive is locked. PRBSCHK_AA PRBS Check Pass/ Fail Indication, Bank A, Channel A. When PRBSCHK_AA = 0, then it is a pass indication. PRBSCHK_AB PRBS Check Pass/ Fail Indication, Bank A, Channel B. When PRBSCHK_AB = 0, then it is a pass indication. PRBSCHK_AC PRBS Check Pass/ Fail Indication, Bank A, Channel C. When PRBSCHK_AC = 0, then it is a pass indication. PRBSCHK_AD PRBS Check Pass/ Fail Indication, Bank A, Channel D. When PRBSCHK_AD = 0, then it is a pass indication. PRBSTOUT_AA PRBS Checker Watchdog Timer Time-Out Alarm, Bank A, Channel A. When PRBSTOUT_AA = 1, then timeout has occurred. PRBSTOUT_AB PRBS Checker Watchdog Timer Time-Out Alarm, Bank A, Channel B. When PRBSTOUT_AB = 1, then timeout has occurred. PRBSTOUT_AC PRBS Checker Watchdog Timer Time-Out Alarm, Bank A, Channel C. When PRBSTOUT_AC = 1, then timeout has occurred. PRBSTOUT_AD PRBS Checker Watchdog Timer Time-Out Alarm, Bank A, Channel D. When PRBSTOUT_AD = 1, then timeout has occurred. -- -- -- -- 00
30010
--
--
--
--
00
30020
--
--
--
--
00
30030
--
--
--
--
00
SERDES A Alarm Mask Registers 30001 MSDON_AA Mask Receive Signal Detect Output, Bank A, Channel A. MSDON_AB Mask Receive Signal Detect Output, Bank A, Channel B. MSDON_AC Mask Receive Signal Detect Output, Bank A, Channel C. MSDON_AD Mask Receive Signal Detect Output, Bank A, Channel D. MLKI_AA Mask Receive PLL Lock Indication, Bank A, Channel A. MLKI_AB Mask Receive PLL Lock Indication, Bank A, Channel B. MLKI_AC Mask Receive PLL Lock Indication, Bank A, Channel C. MLKI_AD Mask Receive PLL Lock Indication, Bank A, Channel D. MPRBSCHK_AA. Mask PRBS Check Pass/Fail Indication, Bank A, Channel A. MPRBSCHK_AB. Mask PRBS Check Pass/Fail Indication, Bank A, Channel B. MPRBSCHK_AC. Mask PRBS Check Pass/Fail Indication, Bank A, Channel C. MPRBSCHK_AD. Mask PRBS Check Pass/Fail Indication, Bank A, Channel D. MPRBSTOUT_AA Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank A, Channel A. MPRBSTOUT_AB Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank A, Channel B. MPRBSTOUT_AC Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank A, Channel C. MPRBSTOUT_AD Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank A, Channel D. -- -- -- -- FF
30011
--
--
--
--
FF
30021
--
--
--
--
FF
30031
--
--
--
--
FF
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Transmit Channel Configuration Registers 30002 TXHR_AA Transmit Half Rate Selection Bit, Bank A, Channel A. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. TXHR_AB Transmit Half Rate Selection Bit, Bank A, Channel B. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. TXHR_AC Transmit Half Rate Selection Bit, Bank A, Channel C. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. PWRDNT_AA Transmit Powerdown Control Bit, Bank A, Channel A. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset. PE0_AA Transmit Preemphasis Selection Bit 0, Bank A, Channel A. PE0, together with PE1, selects one of three preemphasis settings for the transmit section. PE0 = 0 on device reset. PE1_AA Transmit Preemphasis Selection Bit 1, Bank A, Channel A. PE1, together with PE0, selects one of three preemphasis settings for the transmit section. PE1 = 0 on device reset. HAMP_AA Transmit Half Amplitude Selection Bit, Bank A, Channel A. When HAMP = 1, the transmit output buffer voltage swing is limited to half its amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. TBCKSEL_AA Transmit Byte Clock Selection Bit, Bank A, Channel A. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device serset. RINGOVR_AA Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank A, Channel A. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset. 8B10BT_AA Transmit 8B/ 10B Encoder Enable Bit, Bank A, Channel A. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset. 00
30012
PWRDNT_AB Transmit Powerdown Control Bit, Bank A, Channel B. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset.
PE0_AB Transmit Preemphasis Selection Bit 0, Bank A, Channel B. PE0, together with PE1, selects one of three preemphasis settings for the transmit section. PE0 = 0 on device reset.
PE1_AB Transmit Preemphasis Selection Bit 1, Bank A, Channel B. PE1, together with PE0, selects one of three preemphasis settings for the transmit section. PE1 = 0 on device reset.
HAMP_AB Transmit Half Amplitude Selection Bit, Bank A, Channel B. When HAMP = 1, the transmit output buffer voltage swing is limited to half its amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset.
TBCKSEL_AB Transmit Byte Clock Selection Bit, Bank A, Channel B. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device serset.
RINGOVR_AB Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank A, Channel B. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset.
8B10BT_AB Transmit 8B/ 10B Encoder Enable Bit, Bank A, Channel B. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
00
30022
PWRDNT_AC Transmit Powerdown Control Bit, Bank A, Channel C. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset.
PE0_AC Transmit Preemphasis Selection Bit 0, Bank A, Channel C. PE0, together with PE1, selects one of three preemphasis settings for the transmit section. PE0 = 0 on device reset.
PE1_AC Transmit Preemphasis Selection Bit 1, Bank A, Channel C. PE1, together with PE0, selects one of three preemphasis settings for the transmit section. PE1 = 0 on device reset.
HAMP_AC Transmit Half Amplitude Selection Bit, Bank A, Channel C. When HAMP = 1, the transmit output buffer voltage swing is limited to half its amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset.
TBCKSEL_AC Transmit Byte Clock Selection Bit, Bank A, Channel C. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device serset.
RINGOVR_AC Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank A, Channel C. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset.
8B10BT_AC Transmit 8B/ 10B Encoder Enable Bit, Bank A, Channel C. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
00
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Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Transmit Channel Configuration Registers (Continued) 30032 TXHR_AD Transmit Half Rate Selection Bit, Bank A, Channel D. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. PWRDNT_A D Transmit Powerdown Control Bit, Bank A, Channel D. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset. PE0_AD Transmit Preemphasis Selection Bit 0, Bank A, Channel D. PE0, together with PE1, selects one of three preemphasis settings for the transmit section. PE0 = 0 on device reset. PE1_AD Transmit Preemphasis Selection Bit 1, Bank A, Channel D. PE1, together with PE0, selects one of three preemphasis settings for the transmit section. PE1 = 0 on device reset. HAMP_AD Transmit Half Amplitude Selection Bit, Bank A, Channel D. When HAMP = 1, the transmit output buffer voltage swing is limited to half its amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. TBCKSEL_A D Transmit Byte Clock Selection Bit, Bank A, Channel D. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device reset. RINGOVR_A D Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank A, Channel D. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset. 8B10BT_AD Transmit 8B/ 10B Encoder Enable Bit, Bank A, Channel D. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset. 00
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Receive Channel Configuration Registers 30003 RXHR_AA Receive Half Rate Selection Bit, Bank A, Channel A. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset. PWRDNR_AA Receiver Power Down Control Bit, Bank A, Channel A. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset. SDOVRIDE_AA Receive Signal Detect Alarm Override Bit, Bank A, Channel A. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_AB Receive Signal Detect Alarm Override Bit, Bank A, Channel B. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_AC Receive Signal Detect Alarm Override Bit, Bank A, Channel C. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_AD Receive Signal Detect Alarm Override Bit, Bank A, Channel D. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. 8B10BR_AA Receive 8B/10B Decoder Enable Bit, Bank A, Channel A. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset. LINKSM_AA Link State Machine Enable Bit, Bank A, Channel A. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset. -- -- -- 04
30013
RXHR_AB Receive Half Rate Selection Bit, Bank A, Channel B. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_AB Receiver Power Down Control Bit, Bank A, Channel B. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_AB Receive 8B/10B Decoder Enable Bit, Bank A, Channel B. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_AB Link State Machine Enalbe Bit, Bank A, Channel B. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
30023
RXHR_AC Receive Half Rate Selection Bit, Bank A, Channel C. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_AC Receiver Power Down Control Bit, Bank A, Channel C. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_AC Receive 8B/10B Decoder Enable Bit, Bank A, Channel C. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_AC Link State Machine Enalbe Bit, Bank A, Channel C. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
30033
RXHR_AD Receive Half Rate Selection Bit, Bank A, Channel D. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_AD Receiver Power Down Control Bit, Bank A, Channel D. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_AD Receive 8B/10B Decoder Enable Bit, Bank A, Channel D. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_AD Link State Machine Enalbe Bit, Bank A, Channel D. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
40
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Common Transmit and Receive Channel Configuration Registers 30004 PRBS_AA Transmit and Receive PRBS Enable Bit, Bank A, Channel A. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset. MASK_AA Transmit and Receive Alarm Mask Bit, Bank A, Channel A. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset. SWRST_AA Transmit and Receive Software Reset Bit, Bank A, Channel A. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_AB Transmit and Receive Software Reset Bit, Bank A, Channel B. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_AC Transmit and Receive Software Reset Bit, Bank A, Channel C. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_AD Transmit and Receive Software Reset Bit, Bank A, Channel D. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. -- -- -- -- TESTEN_AA Transmit and Receive Test Enable Bit, Bank A, Channel A. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_AB Transmit and Receive Test Enable Bit, Bank A, Channel B. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_AC Transmit and Receive Test Enable Bit, Bank A, Channel C. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_AD Transmit and Receive Test Enable Bit, Bank A, Channel D. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. 02
30014
PRBS_AB Transmit and Receive PRBS Enable Bit, Bank A, Channel B. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset.
MASK_AB Transmit and Receive Alarm Mask Bit, Bank A, Channel B. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset.
--
--
--
--
02
30024
PRBS_AC Transmit and Receive PRBS Enable Bit, Bank A, Channel C. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset.
MASK_AC Transmit and Receive Alarm Mask Bit, Bank A, Channel C. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset.
--
--
--
--
02
30034
PRBS_AD Transmit and Receive PRBS Enable Bit, Bank A, Channel D. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset.
MASK_AD Transmit and Receive Alarm Mask Bit, Bank A, Channel D. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset.
--
--
--
--
02
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES A Global Control Register (Acts on Channels A, B, C, and D) 30005 GPRBS_A Global Enable. The GPRBS bit globally enables the PRBS generators and checkers all four channels of SERDES A when GPRBS = 1. GPRBS = 0 on device reset. GMASK_A Global Mask. The GMASK globally masks all the channel alarms of SERDES A when GMASK = 1. This prevents all the transmit and receive alarms from generating an interrupt. GMASK = 1 on device reset. GSWRST_A RESET Function. The GSWRST bit provides the same function as the hardware reset for the transmit and receive sections of all four channels of ASERDES A, except that the device configuration settings are not affected when GSWRST is asserted. GSWRST = 0 on device reset. This is not a self-clearing bit. Once set, it must be cleared by writing a 0 to it. GPWRDNT_A Powerdown Transmit Function. When GPWRDNT = 1, sections of the transmit hardware for all four channels of SERDES A are powered down to conserve power. GPWRDNT = 0 on device reset. GPWRDNR_A Powerdown Receive Function. When GPWRDNR = 1, sections of the receive hardware for all four channels of SERDES A are powered down to conserve power. GPWRDNR = 0 on device reset. GTRISTN_ A Active-Low TRISTN Function. When GTRISTN = 0, the CMOS output buffers for SERDES A are 3-stated. GTRISTN = 1 on device reset. -- GTESTEN_A Test Enable Control. When GTESTEN = 1, the transmit and receive sections of all four channels of SERDES A are placed in test mode. GTESTEN = 0 on device reset. 022
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Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
Control Registers A 30800 A0 ENBYSYNC_ AA Byte Alignments bank A, channelA LOOPENB_A A Enable loopback mode for bank A, channel A ENBYSYNC_ AB Byte Alignments bank A, channel B LOOPENB_A B Enable loopback mode for bank A, channel B ENBYSYNC_ AC Byte Alignments bank A, channel C LOOPENB_A C Enable loopback mode for bank A, channel C ENBYSYNC_ AD Byte Alignments bank A, channel D LOOPENB_A D Enable loopback mode for bank A, channel D LCKREFN_A A Lock receiver to ref. clock for bank A channel A NOWDALIGN _AA Defeats deMUX alignment for bank A, channel A LCKREFN_A B Lock receiver to ref. clock for bank A channel B NOWDALIGN _AB Defeats deMUX alignment for bank A, channel B LCKREFN_A C Lock receiver to ref. clock for bank A channel C NOWDALIGN _AC Defeats deMUX alignment for bank A, channel C LCKREFN_A D Lock receiver to ref. clock for bank A channel D NOWDALIGN _AD Defeats deMUX alignment for bank A, channel 00
30801
A1
00
30802 30803 30810
A2 A3 A4 DOWDALIGN _AA Force new deMUX word alignment for bank A, channel A DOWDALIGN _AB Force new deMUX word alignment for bank A, channel B DOWDALIGN _AC Force new deMUX word alignment for bank A, channel C
Reserved for future use Reserved for future use DOWDALIGN _AD Force new deMUX word alignment for bank A, channel D FMPU_STR_ EN _AA Enable alignment function for channel AA FMPU_STR_ EN _AB Enable alignment function for channel AB FMPU_STR_ EN_AC Enable alignment function for channel AC FMPU_STR_ EN_AD Enable alignment function for channel AD 00
30811 30812 30813 30820
A5 A6 A7 A8
FMPU_SYNMODE_AA Sync mode for AA
FMPU_SYNMODE_AB Sync mode for AB
FMPU_SYNMODE_AC Sync mode for AC Reserved for future use Reserved for future use
FMPU_SYNMODE_AD Sync mode for AD
00
FMPU_RESY NC1_AA Resync a single channel, AA. Write a 0, then write a 1.
FMPU_RESY NC1_AB Resync a single channel, AB. Write a 0, then write a 1.
FMPU_RESY NC1_AC Resync a single channel, AC. Write a 0, then write a 1.
FMPU_RESY NC1_AD Resync a single channel, AD. Write a 0, then write a 1.
FMPU_RESY NC2_A1 Resync 2 channels, AA and AB. Write a 0, then write a 1.
FMPU_RESY NC2A2 Resync 2 channels, AC and AD. Write a 0, then write a 1.
FMPU_RESY NC4A Resync 4 channels A[A:D]. Write a 0, then write a 1.
XAUI_MODE A Controls use of XAUI link state machine vs. SERDES link State machine for bank A
00
30821
A9
NOCHALGN A Bypass channel alignment demuxed data directly to FPGA for bank A
Reserved for future use
00
30822 30823 30830 30831 30832 30833
A10 A11 A12 A13 A14 A15
Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex)
30804
Reg #
A16
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value 00
00
Status Registers A XAUISTAT_AA* Status of XAUI link state machine for bank A, channel A DEMUXWAS_ AA Status of deMUX word alignment for bank A, channel A DEMUXWAS_ AB Status of deMUX word alignment for bank A, channel B XAUISTAT_AB* Status of XAUI link state machine for bank A, channel B DEMUXWAS_ AC Status of deMUX word alignment for bank A, channel C DEMUXWAS _AD Status of deMUX word alignment for bank A, channel D XAUISTAT_AC* Status of XAUI link state machine for bank A, channel C CH248_SYNC _AA Alignment completed for AA CH248_SYNC _AB Alignment completed for AB XAUISTAT_AD* Status of XAUI link state machine for bank A, channel D CH248_SYNC _AC Alignment completed for AC CH248_SYNC _AD Alignment completed for AD
30805
A17
30806 30807 30814
A18 A19 A20 SYNC2_A1 OVFL Alignment FIFO overflow AA and AB SYNC2_A2 OVFL Alignment FIFO overflow AC and AD SYNC4_A OVFL Alignment FIFO overflow for A[A:D]
Reserved for future use Reserved for future use SYNC2_A1 OOS Alignment out of sync for AA and AB SYNC2_A2 OOS Alignment out of sync for AC and AD SYNC4_A_O OS Alignment out of sync for A[A:D] Reserved for future use
30815 30816 30817 30824 30825 30826 30827 30834 30835 30836 30837
A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use
* For XAUISTAT_Ay (address 0x30804), the definitions of these bits are: 00--No synchronization. 01--Synchronization done. 10--Synchronization done no comma has been detected. 11--Not used.
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Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex)
30100
Reg #
DB0
DB1
DB2
DB3
DB4 DB5 DB6 DB7 Default Value
-- -- -- --
SERDES B Alarm Registers (Read Only) SDON_BA Receive Signal Detect Output, Bank B, Channel A. When SDON_BA = 0, then active data is present. LKI_BA Receive PLL Lock Indication, Bank B, Channel A. When LKI_BA = 1, then PLL receive is locked. PRBSCHK_BA PRBS Check Pass/Fail Indication, Bank B, Channel A. When PRBSCHK_BA = 0, then it is a pass indication. PRBSTOUT_BA PRBS Checker Watchdog Timer Time-Out Alarm, Bank B, Channel A. When PRBSTOUT_BA = 1, then timeout has occurred. PRBSTOUT_BB PRBS Checker Watchdog Timer Time-Out Alarm, Bank B, Channel B. When PRBSTOUT_BB = 1, then timeout has occurred. PRBSTOUT_BC PRBS Checker Watchdog Timer Time-Out Alarm, Bank B, Channel C. When PRBSTOUT_BC = 1, then timeout has occurred. PRBSTOUT_BD PRBS Checker Watchdog Timer Time-Out Alarm, Bank B, Channel D. When PRBSTOUT_BD = 1, then timeout has occurred.
00
30110
SDON_BB Receive Signal Detect Output, Bank B, Channel B. When SDON_BB = 0, then active data is present. SDON_BC Receive Signal Detect Output, Bank B, Channel C. When SDON_BC = 0, then active data is present.
LKI_BB Receive PLL Lock Indication, Bank B, Channel B. When LKI_BB = 1, then PLL receive is locked.
PRBSCHK_BB PRBS Check Pass/Fail Indication, Bank B, Channel B. When PRBSCHK_BB = 0, then it is a pass indication. PRBSCHK_BC PRBS Check Pass/Fail Indication, Bank B, Channel C. When PRBSCHK_BC = 0, then it is a pass indication.
--
--
--
--
00
30120
LKI_BC Receive PLL Lock Indication, Bank B, Channel C. When LKI_BC = 1, then PLL receive is locked.
--
--
--
--
00
30130
SDON_BD Receive Signal Detect Output, Bank B, Channel D. When SDON_BD = 0, then active data is present.
LKI_BD Receive PLL Lock Indication, Bank B, Channel D. When LKI_BD = 1, then PLL receive is locked.
PRBSCHK_BD PRBS Check Pass/Fail Indication, Bank B, Channel D. When PRBSCHK_BD = 0, then it is a pass indication.
--
--
--
--
00
SERDES B Alarm Mask Registers 30101 MSDON_BA Mask Receive Signal Detect Output, Bank B, Channel A. MSDON_BB Mask Receive Signal Detect Output, Bank B, Channel B. MSDON_BC Mask Receive Signal Detect Output, Bank B, Channel C. MSDON_BD Mask Receive Signal Detect Output, Bank B, Channel D. MLKI_BA Mask Receive PLL Lock Indication, Bank B, Channel A. MLKI_BB Mask Receive PLL Lock Indication, Bank B, Channel B. MLKI_BC Mask Receive PLL Lock Indication, Bank B, Channel C. MLKI_BD Mask Receive PLL Lock Indication, Bank B, Channel D. MPRBSCHK_BA. Mask PRBS Check Pass/Fail Indication, Bank B, Channel A. MPRBSCHK_BB. Mask PRBS Check Pass/Fail Indication, Bank B, Channel B. MPRBSCHK_BC. Mask PRBS Check Pass/Fail Indication, Bank B, Channel C. MPRBSCHK_BD. Mask PRBS Check Pass/Fail Indication, Bank B, Channel D. MPRBSTOUT_BA Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank B, Channel A. MPRBSTOUT_BB Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank B, Channel B. MPRBSTOUT_BC Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank B, Channel C. MPRBSTOUT_BD Mask PRBS Checker Watchdog Timer TimeOut Alarm, Bank B, Channel D. -- -- -- --
FF
30111
--
--
--
--
FF
30121
--
--
--
--
FF
30131
--
--
--
--
FF
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr Reg (Hex) #
30102
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value 00
SERDES B Transmit Channel Configuration Registers TXHR_BA Transmit Half Rate Selection Bit, Bank B, Channel A. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. TXHR_BB Transmit Half Rate Selection Bit, Bank B, Channel B. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. TXHR_BC Transmit Half Rate Selection Bit, Bank B, Channel C. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. PWRDNT_BA Transmit Powerdown Control Bit, Bank B, Channel A. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset. PE0_BA PE1_BA HAMP_BA Transmit Preem- Transmit Preem- Transmit Half phasis Selecphasis SelecAmplitude tion Bit 0, Bank tion Bit 1, Bank Selection Bit, B, Channel A. B, Channel A. Bank B, ChanPE0, together PE1, together nel A. When with PE1, with PE0, HAMP = 1, the selects one of selects one of transmit output three preempha- three preempha- buffer voltage sis settings for sis settings for swing is limited the transmit sec- the transmit sec- to half its amplition. PE0 = 0 on tion. PE1 = 0 on tude. Otherdevice reset. device reset. wise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. PE0_BB PE1_BB HAMP_BB Transmit Preem- Transmit Preem- Transmit Half phasis Selecphasis SelecAmplitude tion Bit 0, Bank tion Bit 1, Bank Selection Bit, B, Channel B. B, Channel B. Bank B, ChanPE0, together PE1, together nel B. When with PE1, with PE0, HAMP = 1, the selects one of selects one of transmit output three preempha- three preempha- buffer voltage sis settings for sis settings for swing is limited the transmit sec- the transmit sec- to half its amplition. PE0 = 0 on tion. PE1 = 0 on tude. Otherdevice reset. device reset. wise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. PE0_BC PE1_BC HAMP_BC Transmit Preem- Transmit Preem- Transmit Half phasis Selecphasis SelecAmplitude tion Bit 0, Bank tion Bit 1, Bank Selection Bit, B, Channel C. B, Channel C. Bank B, ChanPE0, together PE1, together nel C. When with PE1, with PE0, HAMP = 1, the selects one of selects one of transmit output three preempha- three preempha- buffer voltage sis settings for sis settings for swing is limited the transmit sec- the transmit sec- to half its amplition. PE0 = 0 on tion. PE1 = 0 on tude. Otherdevice reset. device reset. wise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. TBCKSEL_BA Transmit Byte Clock Selection Bit, Bank B, Channel A. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device reset. RINGOVR_BA Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank B, Channel A. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset. 8B10BT_BA Transmit 8B/10B Encoder Enable Bit, Bank B, Channel A. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
30112
PWRDNT_BB Transmit Powerdown Control Bit, Bank B, Channel B. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset.
TBCKSEL_BB Transmit Byte Clock Selection Bit, Bank B, Channel B. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device reset.
RINGOVR_BB Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank B, Channel B. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset.
8B10BT_BB Transmit 8B/10B Encoder Enable Bit, Bank B, Channel B. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
00
30122
PWRDNT_BC Transmit Powerdown Control Bit, Bank B, Channel C. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset.
TBCKSEL_BC Transmit Byte Clock Selection Bit, Bank B, Channel C. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device reset.
RINGOVR_BC Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank B, Channel C. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset.
8B10BT_BC Transmit 8B/10B Encoder Enable Bit, Bank B, Channel C. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
00
46
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr Reg (Hex) #
30132
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value 00
SERDES B Transmit Channel Configuration Registers (Continued) TXHR_BD Transmit Half Rate Selection Bit, Bank B, Channel D. When TXHR = 1, the transmitter samples data on the falling edge of the TBC clock. When TXHR = 0, the transmitter samples data on the falling edge of the double rate clock (derived from TBC). TXHR = 0 on device reset. PWRDNT_BD Transmit Powerdown Control Bit, Bank B, Channel D. When PWRDNT = 1, sections of the transmit hardware are powered down to conserve power. PWRDNT = 0 on device reset. PE0_BD Transmit Preemphasis Selection Bit 0, Bank B, Channel D. PE0, together with PE1, selects one of three preemphasis settings for the transmit section. PE0 = 0 on device reset. PE1_BD Transmit Preemphasis Selection Bit 1, Bank B, Channel D. PE1, together with PE0, selects one of three preemphasis settings for the transmit section. PE1 = 0 on device reset. HAMP_BD Transmit Half Amplitude Selection Bit, Bank B, Channel D. When HAMP = 1, the transmit output buffer voltage swing is limited to half its amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP = 0 on device reset. TBCKSEL_BD Transmit Byte Clock Selection Bit, Bank B, Channel D. When TBCKSEL = 0, the internal XCK is selected. Otherwise, the TBC clock is selected. TBCKSEL = 0 on device reset. RINGOVR_BD Transmit Ring Counter Bubble Detector Alarm Override Control Bit, Bank B, Channel D. When RINGOVR = 0, the bubble detector alarm is effective. Otherwise, the bubble detector alarm is not effective. RINGOVR = 0 on device reset. 8B10BT_BD Transmit 8B/10B Encoder Enable Bit, Bank B, Channel D. When 8B10BT = 1, the 8B/10B encoder on the transmit path is enabled. Otherwise, it is bypassed. 8B10BT = 0 on device reset.
Agere Systems Inc.
47
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr Reg (Hex) #
30103
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7 Default Value
-- 04
SERDES B Receive Channel Configuration Registers RXHR_BA Receive Half Rate Selection Bit, Bank B, Channel A. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset. PWRDNR_BA Receiver Power Down Control Bit, Bank B, Channel A. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset. SDOVRIDE_BA Receive Signal Detect Alarm Override Bit, Bank B, Channel A. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_BB Receive Signal Detect Alarm Override Bit, Bank B, Channel B. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_BC Receive Signal Detect Alarm Override Bit, Bank B, Channel C. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. SDOVRIDE_BD Receive Signal Detect Alarm Override Bit, Bank B, Channel D. When SDOVRIDE = 1, the energy detector output from the receiver is masked. Thus, when there is no receive data, the powerdown function is disabled and the corresponding SDON alarm is suppressed. SDOVRIDE = 1 on device reset. 8B10BR_BA Receive 8B/10B Decoder Enable Bit, Bank B, Channel A. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset. LINKSM_BA Link State Machine Enalbe Bit, Bank B, Channel A. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset. -- --
30113
RXHR_BB Receive Half Rate Selection Bit, Bank B, Channel B. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_BB Receiver Power Down Control Bit, Bank B, Channel B. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_BB Receive 8B/10B Decoder Enable Bit, Bank B, Channel B. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_BB Link State Machine Enalbe Bit, Bank B, Channel B. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
30123
RXHR_BC Receive Half Rate Selection Bit, Bank B, Channel C. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_BC Receiver Power Down Control Bit, Bank B, Channel C. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_BC Receive 8B/10B Decoder Enable Bit, Bank B, Channel C. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_BC Link State Machine Enalbe Bit, Bank B, Channel C. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
30133
RXHR_BD Receive Half Rate Selection Bit, Bank B, Channel D. When RXHR = 1, the RBC[1:0] clocks are issued at half the scheduled rate of the reference clock. RXHR = 0 on device reset.
PWRDNR_BD Receiver Power Down Control Bit, Bank B, Channel D. When PWRDNR = 1, sections of the receive hardware are powered down to conserve power. PWRDNR = 0 on device reset.
8B10BR_BD Receive 8B/10B Decoder Enable Bit, Bank B, Channel D. When 8B10BR = 1, the 8B/10B decoder on the receive path is enabled. Otherwise, it is bypassed. 8B10BR = on device reset.
LINKSM_BD Link State Machine Enalbe Bit, Bank B, Channel D. When LINKSM = 1, the receiver link state machine is enabled. Otherwise, the link state machine is disables. LINKSM = 0 on device reset.
--
--
--
04
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES B Common Transmit and Receive Channel Configuration Registers 30104 PRBS_BA Transmit and Receive PRBS Enable Bit, Bank B, Channel A. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset. PRBS_BB Transmit and Receive PRBS Enable Bit, Bank B, Channel B. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset. PRBS_BC Transmit and Receive PRBS Enable Bit, Bank B, Channel C. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset. PRBS_BD Transmit and Receive PRBS Enable Bit, Bank B, Channel D. When PRBS = 1, the PRBS generator on the transmitter and the PRBS checker on the receiver are enabled. PRBS = 0 on device reset. MASK_BA Transmit and Receive Alarm Mask Bit, Bank B, Channel A. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset. MASK_BB Transmit and Receive Alarm Mask Bit, Bank B, Channel B. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset. MASK_BC Transmit and Receive Alarm Mask Bit, Bank B, Channel C. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset. MASK_BD Transmit and Receive Alarm Mask Bit, Bank B, Channel D. When MASK = 1, the transmit and receive alarms of a channel are prevented from generating an interrupt. This MASK bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK = 1 on device reset. SWRST_BA Transmit and Receive Software Reset Bit, Bank B, Channel A. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_BB Transmit and Receive Software Reset Bit, Bank B, Channel B. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_BC Transmit and Receive Software Reset Bit, Bank B, Channel C. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. SWRST_BD Transmit and Receive Software Reset Bit, Bank B, Channel D. When SWRST = 1, this bit provides the same function as the hardware reset, except all configuration register settings are preserved. This is not a self-clearing bit. Once set, this bit must be cleared by writing a 0 to it. SWRST = 0 on device reset. -- -- -- -- TESTEN_BA Transmit and Receive Test Enable Bit, Bank B, Channel A. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_BB Transmit and Receive Test Enable Bit, Bank B, Channel B. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_BC Transmit and Receive Test Enable Bit, Bank B, Channel C. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. TESTEN_BD Transmit and Receive Test Enable Bit, Bank B, Channel D. When TESTEN = 1, the transmit and receive sections are placed in test mode. TESTEN = 0 on device reset. When the global test enable bit GTESTEN = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = 1, all channels are set to test mode regardless of their TESTEN setting. 02
30114
--
--
--
--
02
30124
--
--
--
--
02
30134
--
--
--
--
02
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex) Reg # DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Default Value
SERDES B Global Control Register (Acts on Channels A, B, C, and D) 30105 GPRBS_B Global Enable. The GPRBS bit globally enables the PRBS generators and checkers all four channels of SERDES B when GPRBS = 1. GPRBS = 0 on device reset. GMASK_B Global Mask. The GMASK globally masks all the channel alarms of SERDES B when GMASK = 1. This prevents all the transmit and receive alarms from generating an interrupt. GMASK = 1 on device reset. GSWRST_B RESET Function. The GSWRST bit provides the same function as the hardware reset for the transmit and receive sections of all four channels of ASERDES B, except that the device configuration settings are not affected when GSWRST is asserted. GSWRST = 0 on device reset. This is not a self-clearing bit. Once set, it must be cleared by writing a 0 to it. GPWRDNT_B Powerdown Transmit Function. When GPWRDNT = 1, sections of the transmit hardware for all four channels of SERDES B are powered down to conserve power. GPWRDNT = 0 on device reset. GPWRDNR_B Powerdown Receive Function. When GPWRDNR = 1, sections of the receive hardware for all four channels of SERDES B are powered down to conserve power. GPWRDNR = 0 on device reset. GTRISTN_B Active-Low TRISTN Function. When GTRISTN = 0, the CMOS output buffers for SERDES B are 3-stated. GTRISTN = 1 on device reset. -- GTESTEN_B Test Enable Control. When GTESTEN = 1, the transmit and receive sections of all four channels of SERDES B are placed in test mode. GTESTEN = 0 on device reset. 22
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr Reg (Hex) #
Control Registers B 30900 B0 ENBYSYNC_B A Byte Alignments bank B, channel A LOOPENB_BA Enable loopback mode for bank B, channel A ENBYSYNC_B B Byte Alignments bank B, channel B LOOPENB_BB Enable loopback mode for bank B, channel B ENBYSYNC_B C Byte Alignments bank B, channel C LOOPENB_BC Enable loopback mode for bank B, channel C ENBYSYNC_B D Byte Alignments bank B, channel D LOOPENB_BD Enable loopback mode for bank B, channel D LCKREFN_BA Lock receiver to ref. clock for bank B channel A NOWDALIGN_ BA Defeats deMUX alignment for bank B, channel A LCKREFN_BB Lock receiver to ref. clock for bank B channel B NOWDALIGN_ BB Defeats deMUX alignment for bank B, channel B LCKREFN_BC Lock receiver to ref. clock for bank B channel C NOWDALIGN_ BC Defeats deMUX alignment for bank B, channel C LCKREFN_BD Lock receiver to ref. clock for bank B channel D NOWDALIGN_ BD Defeats deMUX alignment for bank B, channel D 00
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value
30901
B1
00
30902 30903 30910
B2 B3 B4 DOWDALIGN_ BA Force new deMUX word alignment for bank B, channel A DOWDALIGN_ BB Force new deMUX word alignment for bank B, channel B DOWDALIGN _BC Force new deMUX word alignment for bank B, channel C
Reserved for future use Reserved for future use DOWDALIGN_ BD Force new deMUX word alignment for bank B, channel D FMPU_STR_E N_BA Enable alignment function for channel BA FMPU_STR_E_ BB Enable alignment function for channel BB FMPU_STR_E N_BC Enable alignment function for channel BC FMPU_STR_E N_BD Enable alignment function for channel BD 00
30911 30912 30913 30920
B5 B6 B7 B8
FMPU_SYNMODE_BA Sync mode for BA
FMPU_SYNMODE_BB Sync mode for BB
FMPU_SYNMODE_BC Sync mode for BC Reserved for future use Reserved for future use
FMPU_SYNMODE_BD Sync mode for BD
00
FMPU_RESYN C1_BA Resync a single channel, BA. Write a 0, then write a 1. NOCHALGN B Bypass channel alignment deMUXed data directly to FPGA for bank B
FMPU_RESYN C1_BB Resync a single channel, BB. Write a 0, then write a 1.
FMPU_RESYN C1_BC Resync a single channel, BC. Write a 0, then write a 1.
FMPU_RESYN C1_BD Resync a single channel, BD. Write a 0, then write a 1.
FMPU_RESYN C2_B1 Resync 2 channels, BA and BB. Write a 0, then write a 1.
FMPU_RESYN C2_B2 Resync 2 channels, BC and BD. Write a 0, then write a 1.
FMPU_RESYN C4_B Resync 4 channels B[A:D]. Write a 0, then write a 1.
XAUI_MODE B Controls use of XAUI link state machine vs. SERDES link State machine for bank B
00
30921
B9
Reserved for future use
00
30922 30923 30930 30931 30932 30933
B10 B11 B12 B13 B14 B15 Reserved for future use
Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use SCHAR_CHAN Select channel to test SCHAR_TXSEL SCHAR_ENA Select TX Enable Characoption terization of SERDES B
00
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex)
30904
Reg #
B16
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value
00
Status Register B XAUISTAT_BA* Status of XAUI link state machine for bank B, channel A DEMUXWAS_ BA Status of deMUX word alignment for bank B, channel A DEMUXWAS_ BB Status of deMUX word alignment for bank B, channel B XAUISTAT_BB* Status of XAUI link state machine for bank B, channel B DEMUXWAS_ BC Status of deMUX word alignment for bank B, channel C DEMUXWAS_ BD Status of deMUX word alignment for bank B, channel D XAUISTAT_BC* Status of XAUI link state machine for bank B, channel C CH248_SYNC _BA Alignment completed for BA CH248_SYNC _BB Alignment completed for BB XAUISTAT_BD* Status of XAUI link state machine for bank B, channel D CH248_SYNC _BC Alignment completed for BC CH248_SYNC _BD Alignment completed for BD
30905
B17
00
30906 30907 30914
B18 B19 B20 SYNC2_B1_O VFL Alignment FIFO overflow for BA and BB SYNC2_B2_O VFL Alignment FIFO overflow for BD and BC SYNC4_B_OV FL Alignment FIFO overflow for B[A:D]
Reserved for future use Reserved for future use SYNC2_B1_O OS Alignment out of sync for BB and BA SYNC2_B2_O OS Alignment out of sync for BC and BD SYNC4_B_O OS Alignment out of sync for B[A:D] Reserved for Future Use 00
30915 30916 30917 30924 30925 30926 30927 30934 30935 30936 30937
B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31
Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use
* For XAUISTAT_By (address 0x30904), the definitions of these bits are: 00--No synchronization. 01--Synchronization done. 10--Synchronization done no comma has been detected. 11--Not used.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Memory Map (continued)
Table 12. Memory Map (continued)
Addr (Hex)
30A00
Reg #
C0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default Value
00
Common Control Registers TCKSELA Controls source of 78 MHz TCK78 for bank A Reserved for future use RCKSELA Controls source of 78 MHz RCK78 for bank A TCKSELB Controls source of 78 MHz TCK78 for bank B RCKSELB controls source of 78 MHz RCK78 for bank B RX_FIFO_MI N Threshold for low address in RX_FIFO's FMPU_RESY NC8 Resync 8 channels, A[A:D], B[A:D] Reserved for future use
30A01
C1
00
30A02
C2
RX_FIFO_MIN Threshold for low address in RX_FIFO's
00
Common Status Registers 30A04 C4 SYNC8_OVFL Alignment FIFO overflow for A[A:D], B[A:D] SYNC8_OOS Alignment out of sync for A[A:D], B[A:D] Reserved for future use 00
30A05
C5
Reserved for future use
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 13. Absolute Maximum Ratings Parameter Storage Temperature Power Supply Voltage with Respect to Ground Symbol Tstg VDD33 VDDIO VDD15 Input Signal with Respect to Ground Signal Applied to High-impedance Output Maximum Package Body Temperature VIN -- -- Min -65 - 0.3 - 0.3 -- VSS - 0.3 VSS - 0.3 -- Max 150 4.2 4.2 2 VDDIO + 0.3 VDDIO + 0.3 220 Unit C V V V V V C
Recommended Operating Conditions
Table 14. Recommended Operating Conditions Parameter Power Supply Voltage with Respect to Ground* Input Voltages Junction Temperature Symbol VDD33 VDD15 VIN TJ Min 2.7 1.4 VSS - 0.3 - 40 Max 3.6 1.6 VDDIO + 0.3 125 Unit V V V C
* For recommended operating conditions for VDDIO, see the Series 4 FPGA Data Sheet and the Series 4 I/O Buffer Application Note.
HSI Electrical and Timing Characteristics
Table 15. Absolute Maximum Ratings Parameter Power Dissipation Conditions SERDES and I/O (per channel) 8B/10B encoder/decoder (per channel) Min -- -- Typ -- -- Max 225 50 Unit mW mW
Table 16. Recommended Operating Conditions Parameter VDD15 Supply Voltage Conditions -- Min 1.4 Typ -- Max 1.6 Unit V
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
HSI Electrical and Timing Characteristics (continued)
1.2 V
200 mV @ 1.0--2.5 GBits/s, 350 mV @ 3.125 GBits/s
0.4UI
UI
2391(F)
Figure 19. Receive Data Eye-diagram Template (Differential)
Figure 19 provides a graphical characterization of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time lints, noise and jitter limits, and P and N input skew tolerance. it is believed that incoming data patterns falling within the shaded region of the template will be received without error (BER < 10E-12). Data pattern eye-opening at the receive end of a link is considered the ultimate measures of received signal quality. Almost all detrimental characteristics of transmit signal and the interconnection link design result in eye-closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a links ability to transfer data error-free. Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery (CDR) portion of the ORT82G5 SERDES receiver is its ability to filter incoming signal jitter that is below the clock recover bandwidth (estimated to be about 3 MHz). For signals with high levels of low frequency jitter the receiver can detect incoming data, error-free, with eye-openings significantly less than that of Figure 19. This phenomena has been observed in the laboratory. Eye-diagram measurement and simulation are excellent tools of design. They are both highly recommended when designing serial link interconnections and evaluating signal integrity. Table 17. Receiver Specifications Parameter Input Data Stream of Nontransitions Phase change, Input Signal Eye Opening Jitter Tolerance Conditions -- -- -- -- Min -- -- 0.4 Typ -- -- -- TBD Max 60 TBD -- Unit bits ps UIP-P UIP-P
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
HSI Electrical and Timing Characteristics (continued)
Table 18. Reference Clock Specifications (REFINP and REFINN) Parameter Frequency Range Frequency Tolerance Duty Cycle (Measured at 50% Amplitude Point) Rise Time Fall Time Differential Amplitude Common Mode Level Single-Ended Amplitude Input Capacitance (Single Ended) In-band Jitter (2.5 Gbits/s) In-band Jitter (1.25 Gbits/s) Out-of-Band Jitter Table 19. Channel Output Jitter (1.25 Gbits/s) Parameter Deterministic Random Total Table 20. Channel Output Jitter (2.5 Gbits/s) Parameter Deterministic Random Total Table 21. Serial Output Timing Levels (CML I/O) Parameter Rise Time (20%--80%) Fall Time (80%--20%) Common Mode Differential Swing (Full Amplitude) Differential Swing (Half Amplitude) Output Load Table 22. Serial Input Timing and Levels (CML I/O) Parameter Rise Time Fall Time Differential Swing Common Mode Level Signal Detect Threshold 56 Min -- -- 175 0.6 -- Typ 150 150 -- -- TBD Max -- -- 1200 0.9 -- Unit ps ps mVP-P V V Min 100 100 -- 800 400 50 Typ 150 150 1.25 1000 500 -- Max -- -- -- 1200 600 75 Unit ps ps V mVP-P mVP-P Min -- -- -- Typ TBD TBD TBD Max 0.1 0.14 0.24 Unit UIP-P UIP-P UIP-P Min -- -- -- Typ TBD TBD TBD Max 0.08 0.12 0.2 Unit UIP-P UIP-P UIP-P Min 100 - 100 40 -- -- 500 0.5 1.0 -- -- -- -- Typ -- -- 50 -- -- -- -- -- 20 -- -- -- Max 156.25 100 60 500 500 1000 1.0 1.5 -- 20 40 TBD Unit MHz ppm % ps ps mVP-P V V pF psP-P psP-P psP-P
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the userprogrammable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. Table 23. FPGA Common-Function Pin Description Symbol Dedicated Pins VDD33 VDD15 VDDIO GND PTEMP
RESET
I/O -- 3 V positive power supply.
Description
-- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground supply. I I Temperature sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after configuration.* As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
PRGM is an active-low input that forces the restart of configuration and resets the boundary scan circuitry. This pin always has an active pull-up.
CCLK
I O
DONE
I O
PRGM RD_CFG
I I
This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0.
RD_DATA/TDO
CFG_IRQ/MPI_IRQ
O O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Preliminary Data Sheet July 2001
Pin Information (continued)
Table 23. FPGA Common-Function Pin Description (continued)
Symbol M[3:0] I/O I Description During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
Special-Purpose Pins (Can also be used as a general I/O.)
I/O After configuration, these pins are user-programmable I/O.* PLL_CK[0:7] I/O Dedicated PCM clock pins. These pins are user-programmable I/O pins if not used by PLLs. P[TBTR]CLK[1:0][ I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential TC] pairing. They may be used as general I/O pins if not needed for clocking purposes. TDI, TCK, TMS I If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary scan is not selected, all boundary scan functions are inhibited once configuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O.* RDY/BUSY/RCLK O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* I/O During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. HDC O High during configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* LDC O Low during configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.* I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe.
CS0, CS1
I/O After configuration, these pins are user-programmable I/O pins.* RD/MPI_STRB I
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 23. FPGA Common-Function Pin Description (continued)
Symbol PPC_A[14:31] A[17:0] I/O I Description During MPI mode, the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least significant bits of the PowerPC 32-bit address.
MPI_BURST MPI_BDIP
MPI_TSZ[1:0]
A[21:0] MPI_ACK MPI_CLK
O During master parallel configuration mode, A[14:31] address the configuration EPROM. In MPI mode, many of the A[n] pins have alternate uses as described below. See the special function blocks section for more MPI information. During configuration, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled. MPI_BURST is driven low to indicate a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. MPI_BDIP is driven by the PowerPC processor assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[14:31], MPI_BURST, MPI_BDIP and MPI_TSZ address the , configuration EPROMs up to 4 Mbytes. If not used for MPI, these pins are user-programmable I/O pins.* O In PowerPC mode MPI operation, this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA bus clock.
MPI_TEA MPI_RTRY D[0:31]
O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. O This pin requests the MPC860 to relinquish the bus and retry the cycle. I/O Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transaction. Driven by MPI in a read transaction. I D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low. After configuration, the pins are user-programmable I/O pins.*
DP[0:3]
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:32]. After configuration, this pin is a user-programmable I/O pin.* I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled.
DIN
I/O After configuration, this pin is a user-programmable I/O pin.* DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK. I/O After configuration, DOUT is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary. Table 24. FPSC Function Pin Description Symbol I/O Description
Common Signals for Both SERDES A and B PASB_RESETN PASB_TRISTN PASB_PDN PASB_TESTCLK PBIST_TEST_ENN PLOOP_TEST_ENN PMP_TESTCLK PMP_TESTCLK_ENN PSYS_DOBISTN PSYS_RSSIG_ALL SERDES A and B Pins REFCLKN_A REFCLKP_A REFCLKN_B REFCLKP_B REXT_A REXT_B REXTN_A REXTN_B HDINN_AA HDINP_AA HDINN_AB HDINP_AB HDINN_AC HDINP_AC HDINN_AD HDINP_AD HDINN_BA HDINP_BA HDINN_BB HDINP_BB HDINN_BC HDINP_BC HDINN_BD HDINP_BD I I I I I I I I I I I I I I I I I I I I I I I I CML reference clock input--SERDES A. CML reference clock input--SERDES A. CML reference clock input--SERDES B. CML reference clock input--SERDES B. Reference resistor - SERDES A. Reference resistor - SERDES B. Reference resistor - SERDES A. A 3.32 K 1% resistor must be connected across REXT_A and REXTN_A. Reference resistor--SERDES B. A 3.32 K 1% resistor must be connected across REXT_B and REXTN_B. High-speed CML receive data input--SERDES A, channel A. High-speed CML receive data input--SERDES A, channel A. High-speed CML receive data input--SERDES A, channel B. High-speed CML receive data input--SERDES A, channel B. High-speed CML receive data input--SERDES A, channel C. High-speed CML receive data input--SERDES A, channel C. High-speed CML receive data input--SERDES A, channel D. High-speed CML receive data input--SERDES A, channel D. High-speed CML receive data input--SERDES B, channel A. High-speed CML receive data input--SERDES B, channel A. High-speed CML receive data input--SERDES B, channel B. High-speed CML receive data input--SERDES B, channel B. High-speed CML receive data input--SERDES B, channel C. High-speed CML receive data input--SERDES B, channel C. High-speed CML receive data input--SERDES B, channel D. High-speed CML receive data input--SERDES B, channel D. I I I I I I I I I O Reset. 3-state output buffers. Power down. Clock input for BIST and loopback test. Selection of PASB_TESTCLK input for BIST test. Selection of PASB_TESTCLK input for loopback test. Clock input for microprocessor in test mode. Selection of PMP_TESTCLK in test mode. Input to start BIST test. Output result of BIST test.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 24. FPSC Function Pin Description (continued) Symbol SERDES A and B Pins HDOUTN_AA HDOUTP_AA HDOUTN_AB HDOUTP_AB HDOUTN_AC HDOUTP_AC HDOUTN_AD HDOUTP_AD HDOUTN_BA HDOUTP_BA HDOUTN_BB HDOUTP_BB HDOUTN_BC HDOUTP_BC HDOUTN_BD HDOUTP_BD Power and Ground VDDIB_AA VDDIB_AB VDDIB_AC VDDIB_AD VDDIB_BA VDDIB_BB VDDIB_BC VDDIB_BD VDDOB_AA VDDOB_AB -- -- -- -- -- -- -- -- -- -- 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial input buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. O O O O O O O O O O O O O O O O High-speed CML transmit data output--SERDES A, channel A. High-speed CML transmit data output--SERDES A, channel A. High-speed CML transmit data output--SERDES A, channel B. High-speed CML transmit data output--SERDES A, channel B. High-speed CML transmit data output--SERDES A, channel C. High-speed CML transmit data output--SERDES A, channel C. High-speed CML transmit data output--SERDES A, channel D. High-speed CML transmit data output--SERDES A, channel D. High-speed CML transmit data output--SERDES B, channel A. High-speed CML transmit data output--SERDES B, channel A. High-speed CML transmit data output--SERDES B, channel B. High-speed CML transmit data output--SERDES B, channel B. High-speed CML transmit data output--SERDES B, channel C. High-speed CML transmit data output--SERDES B, channel C. High-speed CML transmit data output--SERDES B, channel D. High-speed CML transmit data output--SERDES B, channel D. I/O Description
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 24. FPSC Function Pin Description (continued) Symbol VDDOB_AC VDDOB_AD VDDOB_BA VDDOB_BB VDDOB_BC VDDOB_BD VSSRX_AA VSSRX_AB VSSRX_AC VSSRX_AD VSSRX_BA VSSRX_BB VSSRX_BC VSSRX_BD VSSGB_A VSSGB_B VDDGB_A VDDGB_B VSSAUX_A VSSAUX_B VSSIB_AA VSSIB_AB VSSIB_AC VSSIB_AD VSSIB_BA VSSIB_BB VSSIB_BC VSSIB_BD VSSOB_AA VSSOB_AB VSSOB_AC VSSOB_AD VSSOB_BA VSSOB_BB VSSOB_BC VSSOB_BD VSSTX_AA VSSTX_AB VSSTX_AC VSSTX_AD VSSTX_BA 62 I/O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. 1.8 V/1.5 V power supply for high-speed serial output buffers. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. SERDES analog receive circuitry ground. Guard band ground. Guard band ground. 1.5 V guard band power supply. 1.5 V guard band power supply. SERDES auxiliary circuit ground (no external pin). SERDES auxiliary circuit ground. High-speed input receive buffer ground (no external pin). High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed input receive buffer ground. High-speed output transmit buffer ground (no external pin). High-speed output transmit buffer ground. High-speed output transmit buffer ground. High-speed output transmit buffer ground. High-speed output transmit buffer ground. High-speed output transmit buffer ground. High-speed output transmit buffer ground. High-speed output transmit buffer ground. SERDES analog transmit circuitry ground (no external pin). SERDES analog transmit circuitry ground. SERDES analog transmit circuitry ground. SERDES analog transmit circuitry ground. SERDES analog transmit circuitry ground. Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 24. FPSC Function Pin Description (continued) Symbol VSSTX_BB VSSTX_BC VSSTX_BD VDDRX_AA VDDRX_AB VDDRX_AC VDDRX_AD VDDRX_BA VDDRX_BB VDDRX_BC VDDRX_BD VDDAUX_A VDDAUX_B I/O -- -- -- -- -- -- -- -- -- -- -- -- -- Description SERDES analog transmit circuitry ground. SERDES analog transmit circuitry ground. SERDES analog transmit circuitry ground. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V Power supply for SERDES analog receive circuitry. 1.5 V power supply for SERDES auxiliary circuit. 1.5 V power supply for SERDES auxiliary circuit.
Power Supplies for ORT82G5
Power Supply Descriptions Table 25 shows the ORT82G5 embedded core power supply connection groupings. The Tx-Rx digital power supplies are used for transmit and receive digital logic including the microprocessor logic. The Tx-Rx analog power supplies are used for high-speed analog circuitry between the I/O buffers and the digital logic. The Rx input buffer power supplies are used to power the input (receive) buffers. The Tx output buffer supplies are used to power the output (transmit) buffers. The Rx and Tx buffer power supplies can be independently set to 1.5 V or 1.8 V, depending on the end application. The auxiliary and guard band supplies are independent connection brought out to pins. Table 25. Power Supply Pin Groupings Tx-Rx Digital 1.5 V VDD15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc. Tx-Rx Analog 1.5 V VDDRX_AA VDDTX_AA VDDRX_AB VDDTX_AB VDDRX_AC VDDTX_AC VDDRX_AD VDDTX_AD VDDRX_BA VDDTX_BA VDDRX_BB VDDTX_BB VDDRX_BC VDDTX_BC VDDRX_BD VDDTX_BD Tx Output Rx Input Buffers Buffers 1.5/1.8 V 1.5 V/1.8 V VDDOB_AA VDDOB_AB VDDOB_AC VDDOB_AD VDDOB_BA VDDOB_BB VDDOB_BC VDDOB_BD -- -- -- -- -- -- -- -- VDDIB_AA VDDIB_AB VDDIB_AC VDDIB_AD VDDIB_BA VDDIB_BB VDDIB_BC VDDIB_BD -- -- -- -- -- -- -- -- Auxiliary 1.5 V VDDAUX_A VDDAUX_B -- -- -- -- -- -- -- -- -- -- -- -- -- -- Guard Band 1.5 V VDDGB_A VDDGB_B -- -- -- -- -- -- -- -- -- -- -- -- -- -- 63
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Recommended Power Supply Connections
Ideally, a board should have four separate power supplies as described below:
s
Tx-Rx digital auxiliary supplies.
The Tx-Rx digital and auxiliary power supply nodes should be supplied by a 1.5 V source. A single 1.5 V source can supply power to Tx-Rx digital and auxiliary nodes.
s
Tx-Rx analog, guardband supplies.
A dedicated 1.5 V power supply should be provided to the analog power pins. This will allow the end user to minimize noise. The guard band pins can also be sourced from the analog power supplies.
s
Tx output buffers.
the power supplies to the Tx output buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these output buffers. The power supply can be 1.5 V or 1.8 V depending on the end application.
s
Rx input buffers.
The power supplies to the Rx input buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these input buffers. The power supply can be 1.5 V or 1.8 V depending on the end application.
Recommended Power Supply Filtering Scheme
The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example demonstration board schematic is available at: http://www.agere.com/netcom/platform/fpsc.html#ORT82G5 Power supply filtering is in the form of:
s s
A parallel bypass capacitor network consisting of 10 uf, 0.1 uf, and 1.0 uf caps close to the power source. A parallel bypass capacitor network consisting of 0.01 uf and 0.1 uf close to the pin on the ORT82G5.
Example connections are shown in Figure 20. The naming convention for the power supply sources shown in the figure are as follows:
s s s s s
Supply_1.5 V--Tx-Rx digital, auxiliary power pins. Supply_VDDRX--Rx analog power pins, guard band power pins. Supply VDDTX--Tx analog power pins. Supply VDDIB--Input Rx buffer power pins. Supply_VDDOB--Output Rx buffer power pins.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
SOURCE SUPPLY_1.5 V
PIN VDD15 0.1 f 10 f 1 f 0.01 f 0.1 f
- 1 NETWORK FOR EVERY 2 PINS - 1 NETWORK FOR VDDAUX_[A,B] SUPPLY_VDDRX VDDRX 0.1 f 1 f 0.1 f
10 f
0.01 f
- 1 NETWORK FOR EVERY 2 PINS - 1 EACH FOR VDDGB_[A,B] SUPPLY_VDDTX VDDTX 0.1 f 10 f 1 f 0.01 f 0.1 f
- 1 NETWORK FOR EVERY 2 PINS SUPPLY_VDDIB VDDIB
0.1 f
10 f
1 f
0.01 f
0.1 f
- 1 NETWORK FOR EVERY 2 PINS SUPPLY_VDDOB VDDOB 0.1 f
10 f
1 f
0.01 f
0.1 f
- 1 NETWORK FOR EVERY 2 PINS
2390(F)
Figure 20. Power Supply Filtering
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
In Table 26, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. Table 26. Embedded Core/FPGA Interface Signal Description Pin Name Memory Block Interface Signals AR_A[10:0] AR_B[10:0] AW_A[10:0] AW_B[10:0] BYTEWN_A[3:0] BYTEWN_B[3:0] CKR_A CKR_B CKW_A CKW_B CSR_A CSR_B CSWA_A CSWA_B CSWB_A CSWB_B D_A[35:0] D_B[35:0] Q_A[35:0] Q_B[35:0] I I I I I I I I I I I I I I I I I I O O Read address--memory block A. Read address--memory block B. Write address--memory block A. Write address--memory block B. Write control pins for byte-at-a-time write-memory block A. Write control pins for byte-at-a-time write-memory block B. Read clock--memory block A. Read clock--memory block B. Write clock--memory block A. Write clock--memory block A. Read chip select--memory block A. Read chip select--memory block A. Write chip select A--memory block A. Write chip select A--memory block B. Write chip select B--memory block A. Write chip select B--memory block B. Data in--memory block A Data in--memory block B. Data out--memory block A. Data out--memory block B. I/O Description
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 26. Embedded Core/FPGA Interface Signal Description (continued) Pin Name Transmit Path Signals TWDAA[31:0] TWDAB[31:0] TWDAC[31:0] TWDAD[31:0] TWDBA[31:0] TWDBB[31:0] TWDBC[31:0] TWDBD[31:0] TCOMMAAA[3:0] TCOMMAAB[3:0] TCOMMAAC[3:0] TCOMMAAD[3:0] TCOMMABA[3:0] TCOMMABB[3:0] TCOMMABC[3:0] TCOMMABD[3:0] TCK78A TCK78B TSYSCLKA TSYSCLKB I I I I I I I I I I I I I I I I O O I I Transmit data--SERDES A, channel A. Transmit data--SERDES A, channel B. Transmit data--SERDES A, channel C. Transmit data--SERDES A, channel D. Transmit data--SERDES B, channel A. Transmit data--SERDES B, channel B. Transmit data--SERDES B, channel C. Transmit data--SERDES B, channel D. Transmit comma character--SERDES A, channel A. Transmit comma character--SERDES A, channel B. Transmit comma character--SERDES A, channel C. Transmit comma character--SERDES A, channel D. Transmit comma character--SERDES B, channel A. Transmit comma character--SERDES B, channel B. Transmit comma character--SERDES B, channel C. Transmit comma character--SERDES B, channel D. Transmit low-speed clock to FPGA--SERDES A. Transmit low-speed clock to FPGA--SERDES B. Low-speed transmit FIFO clock--SERDES A. Low-speed transmit FIFO clock--SERDES B. I/O Description
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 26. Embedded Core/FPGA Interface Signal Description (continued) Pin Name Receive Path Signals MRWDAA[39:0] MRWDAB[39:0] MRWDAC[39:0] MRWDAD[39:0] MRWDBA[39:0] MRWDBB[39:0] MRWDBC[39:0] MRWDBD[39:0] RWCKAA RWCKAB RWCKAC RWCKAD RWCKBA RWCKBB RWCKBC RWCKBD RCK78A RCK78A RSYS_CLKA RSYS_CLKB SYS_RST_N O O O O O O O O O O O O O O O O O O I I I Receive data--SERDES A, channel A. Receive data--SERDES A, channel B. Receive data--SERDES A, channel C. Receive data--SERDES A, channel D. Receive data--SERDES B, channel A. Receive data--SERDES B, channel B. Receive data--SERDES B, channel C. Receive data--SERDES B, channel D. Low-speed receive clock--SERDES A, channel A. Low-speed receive clock--SERDES A, channel B. Low-speed receive clock--SERDES A, channel C. Low-speed receive clock--SERDES A, channel D. Low-speed receive clock--SERDES B, channel A. Low-speed receive clock--SERDES B, channel B. Low-speed receive clock--SERDES B, channel C. Low-speed receive clock--SERDES B, channel D. Receive low-speed clock to FPGA--SERDES A. Receive low-speed clock to FPGA--SERDES B. Low-speed receive FIFO clock--SERDES A. Low-speed receive FIFO clock--SERDES B. Synchronous reset of the channel alignment blocks. I/O Description
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Package Pinouts
Table 27 provides the package pin and pin function for the ORT82G5 FPSC and packages. The bond pad name is identified in the PIO nomenclature used in the ORCA Foundry design editor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the FPGA. The tables provide no information on unused pads.
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Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout BM680 AB20 C3 E4 F5 G5 D3 A2 F4 G4 B3 C2 B1 A1 J5 H5 B7 E3 F3 C1 D2 A34 G3 H4 E2 D1 C5 F2 E1 AA13 J4 K5 H3 G2 C9 L5 K4 H2 J3 AA14 M5 F1 G1 70 VDDIO Bank -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) VREF Group -- -- -- -- -- -- -- 7 7 -- 7 7 -- 7 7 -- 8 8 8 8 -- 8 8 9 9 -- 9 9 -- 9 9 9 9 -- 9 9 10 10 -- 10 10 10 I/O Vss VDD33 O I I I VDDIO0 IO IO VDDIO0 IO IO Vss IO IO VDDIO0 IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VSS IO IO IO Pin Description Vss VDD33 PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VDDIO0 PL3D PL3C VSS PL4D PL4C VDDIO0 PL4B PL4A PL5D PL5C VSS PL5B PL5A PL6D PL6C VDDIO0 PL7D PL7C VSS PL7B PL7A PL8D PL8C VDDIO0 PL8B PL8A PL9D PL9C VSS PL9B PL10D PL10C Additional Function -- -- RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- -- VREF_0_07 -- D5 D6 -- -- VREF_0_08 HDC LDC_N -- -- -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 -- -- -- CS0_N CS1 -- -- -- -- -- -- -- INIT_N DOUT BM680 Pair -- -- -- -- -- -- -- L21C_A0 L21T_A0 -- L22C_D0 L22T_D0 -- L23C_A0 L23T_A0 -- L24C_A0 L24T_A0 L25C_D0 L25T_D0 -- L26C_D0 L26T_D0 L27C_D0 L27T_D0 -- L28C_D0 L28T_D0 -- L29C_D0 L29T_D0 L30C_D0 L30T_D0 -- L31C_D0 L31T_D0 L32C_D0 L32T_D0 -- -- L33C_A0 L33T_A0
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Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 K3 J2 AA15 L4 N5 M4 AA3 L3 K2 H1 J1 V18 N4 P5 M3 L2 AC2 K1 L1 P4 P3 V19 M2 M1 N2 N1 N3 R4 P2 R3 W16 R5 P1 R1 T5 T4 T3 T2 W17 U1 T1 U4 VDDIO Bank 0 (TL) 0 (TL) -- 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) VREF Group 10 10 -- 10 1 1 -- 1 1 1 1 -- 2 2 2 2 -- 2 2 2 2 -- 2 2 3 3 -- 3 3 3 -- 3 3 3 3 3 4 4 -- 4 4 4 I/O IO IO VSS IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO VSS IO IO IO IO IO IO IO VSS IO IO IO Pin Description PL11D PL11C VSS PL11B PL12D PL12C VDDIO7 PL12B PL12A PL13D PL13C VSS PL13B PL13A PL14D PL14C VDDIO7 PL14B PL14A PL15D PL15C VSS PL15B PL15A PL16D PL16C VDDIO7 PL16B PL17D PL17C VSS PL17B PL18D PL18C PL18B PL18A PL19D PL19C VSS PL19B PL19A PL20D Additional Function VREF_0_10 A16/PPC_A30 -- -- A15/PPC_A29 A14/PPC_A28 -- -- -- VREF_7_01 D4 -- -- -- RDY/BUSY_N/RCLK VREF_7_02 -- -- -- A13/PPC_A27 A12/PPC_A26 -- -- -- -- -- -- -- A11/PPC_A25 VREF_7_03 -- -- -- -- -- -- RD_N/MPI_STRB_N VREF_7_04 -- -- -- PLCK0C BM680 Pair L34C_D0 L34T_D0 -- -- L1C_D0 L1T_D0 -- L2C_D0 L2T_D0 L3C_A0 L3T_A0 -- L4C_D0 L4T_D0 L5C_D0 L5T_D0 -- L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 L9C_A0 L9T_A0 -- -- L10C_D0 L10T_D0 -- -- L11C_A0 L11T_A0 L12C_A0 L12T_A0 L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 L15C_A0 71
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 U5 R2 U2 V1 W18 V2 V3 W19 V4 V5 W4 W3 W1 Y1 Y2 AA1 Y13 Y4 Y3 Y5 W5 U3 AB1 AA2 AB2 AC1 Y14 AA4 AB4 AB3 W2 AD1 AE1 AD2 AC3 AC4 AF1 AE2 AB5 AA5 Y15 AD3 72 VDDIO Bank 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) VREF Group 4 -- 4 4 -- 5 5 -- 5 5 5 5 5 5 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 6 6 6 -- 7 7 7 7 7 8 8 8 8 -- 8 I/O IO VDDIO7 IO IO VSS IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO VDDIO7 IO IO IO IO IO IO IO IO IO VSS IO Pin Description PL20C VDDIO7 PL20B PL20A VSS PL21D PL21C VSS PL21B PL21A PL22D PL22C PL22B PL22A PL23D PL23C VSS PL23B PL23A PL24D PL24C VDDIO7 PL24B PL24A PL25D PL25C VSS PL25B PL26D PL26C VDDIO7 PL26B PL27D PL27C PL27B PL27A PL28D PL28C PL29D PL29C VSS PL29B Additional Function PLCK0T -- -- -- -- A10/PPC_A24 A9/PPC_A23 -- -- -- A8/PPC_A22 VREF_7_05 -- -- -- -- -- -- -- PLCK1C PLCK1T -- -- -- VREF_7_06 A7/PPC_A21 -- -- A6/PPC_A20 A5/PPC_A19 -- -- WR_N/MPI_RW VREF_7_07 -- -- A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 -- -- BM680 Pair L15T_A0 -- L16C_D0 L16T_D0 -- L17C_A0 L17T_A0 -- L18C_A0 L18T_A0 L19C_A0 L19T_A0 L20C_A0 L20T_A0 L21C_D0 L21T_D0 -- L22C_A0 L22T_A0 L23C_A0 L23T_A0 -- L24C_D0 L24T_D0 L25C_D0 L25T_D0 -- -- L26C_A0 L26T_A0 -- -- L27C_D0 L27T_D0 L28C_A0 L28T_A0 L29C_D0 L29T_D0 L30C_A0 L30T_A0 -- --
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AG1 AF2 AD4 AE3 AD5 AC5 Y20 AG2 AH1 AF3 AG3 AL7 AE4 AF4 AE5 AF5 R21 AJ1 AH2 AM5 AK1 AJ2 R22 AG4 AH3 AL1 AK2 AM9 AM1 AL2 AJ3 T16 AJ4 AH4 AK3 AN2 AG5 AH5 AN1 AM2 T17 AL3 VDDIO Bank 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) VREF Group 8 8 8 8 8 8 -- 8 8 1 1 -- 1 1 1 1 -- 2 2 -- 2 2 -- 3 3 3 3 -- 3 3 4 -- 4 4 4 -- 4 4 4 4 -- 4 I/O IO IO IO IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO VDDIO6 IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO VDDIO6 IO IO IO IO VSS IO Pin Description PL30D PL30C PL30B PL30A PL31D PL31C VSS PL31B PL31A PL32D PL32C VDDIO6 PL32B PL32A PL33D PL33C VSS PL34D PL34C VDDIO6 PL34B PL34A VSS PL35B PL35A PL36D PL36C VDDIO6 PL36B PL36A PL37D VSS PL37B PL37A PL38C VDDIO6 PL38B PL38A PL39D PL39C VSS PL39B Additional Function A1/PPC_A15 A0/PPC_A14 -- -- DP0 DP1 -- -- -- D8 VREF_6_01 -- -- -- D9 D10 -- -- VREF_6_02 -- -- -- -- D11 D12 -- -- -- VREF_6_03 D13 -- -- -- VREF_6_04 -- -- -- -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- BM680 Pair L31C_D0 L31T_D0 L32C_D0 L32T_D0 L33C_A0 L33T_A0 -- L34C_D0 L34T_D0 L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_D0 L4T_D0 -- L5C_D0 L5T_D0 -- L6C_D0 L6T_D0 L7C_D0 L7T_D0 -- L8C_D0 L8T_D0 -- -- L9C_A0 L9T_A0 -- -- L10C_A0 L10T_A0 L11C_D0 L11T_D0 -- L12C_D0 73
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AK4 T18 AM3 AN3 AJ5 AL4 T19 AK5 AM4 AL5 AN7 AP3 AP4 AN4 U16 AK6 AK7 AL6 AM6 AP1 AN5 AP5 AK8 U17 AP6 AP7 AM7 AN6 AP2 AL8 AL9 AK9 U18 AN8 AM8 AN9 AP8 AK10 AL10 AP9 U19 AM10 74 VDDIO Bank 6 (BL) -- -- 6 (BL) -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) VREF Group 4 -- -- -- -- -- -- -- 5 5 -- 5 5 5 -- 5 5 5 5 -- 6 6 6 -- 6 6 6 6 -- 7 7 7 -- 7 7 7 7 7 7 8 -- 8 I/O IO VSS I VDDIO6 IO VDD33 VSS VDD33 IO IO VDDIO6 IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO IO VDDIO6 IO IO IO VSS IO IO IO IO IO IO IO VSS IO Pin Description PL39A VSS PTEMP VDDIO6 LVDS_R VDD33 VSS VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3B VSS PB3C PB3D PB4A PB4B VDDIO6 PB4C PB4D PB5B VSS PB5C PB5D PB6A PB6B VDDIO6 PB6C PB6D PB7B VSS PB7C PB7D PB8A PB8B PB8C PB8D PB9B VSS PB9C Additional Function -- -- PTEMP -- LVDS_R -- -- -- DP2 -- -- PLL_CK6T/PPLL PLL_CK6C/PPLL -- -- -- -- VREF_6_05 DP3 -- -- -- -- -- VREF_6_06 D14 -- -- -- D15 D16 -- -- D17 D18 -- -- VREF_6_07 D19 -- -- D20 BM680 Pair L12T_D0 -- -- -- -- -- -- -- L13T_D0 L13C_D0 -- L14T_A0 L14C_A0 -- -- L15T_A0 L15C_A0 L16T_A0 L16C_A0 -- L17T_A0 L17C_A0 -- -- L18T_D0 L18C_D0 L19T_D0 L19C_D0 -- L20T_A0 L20C_A0 -- -- L21T_A0 L21C_A0 L22T_D0 L22C_D0 L23T_A0 L23C_A0 -- -- L24T_A0
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AM11 AK11 AN10 AP10 AN11 AP11 V16 AL12 AK12 AN12 AM12 AP12 AP13 AM13 AN14 V17 AP14 AP15 AK13 AK14 AM14 AL14 AP17 AP16 AM15 AN16 AM17 AM16 AP18 AP19 AL16 AK15 N22 AN18 AN19 AP20 AP21 AL17 AK16 P13 AM19 AM18 VDDIO Bank 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) VREF Group 8 8 8 8 9 9 -- 9 9 9 9 9 9 9 9 -- 10 10 10 10 10 10 11 11 11 11 11 11 11 11 1 1 -- 1 1 1 1 1 1 -- 2 2 I/O IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO VSS IO IO Pin Description PB9D PB10B PB10C PB10D PB11A PB11B VSS PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B VSS PB13C PB13D PB14A PB14B PB14C PB14D PB15A PB15B PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B VSS PB17C PB17D PB18A PB18B PB18C PB18D VSS PB19A PB19B Additional Function D21 -- VREF_6_08 D22 -- -- -- D23 D24 -- -- VREF_6_09 D25 -- -- -- D26 D27 -- -- VREF_6_10 D28 -- -- D29 D30 -- -- VREF_6_11 D31 -- -- -- -- -- -- -- VREF_5_01 -- -- -- -- BM680 Pair L24C_A0 -- L25T_A0 L25C_A0 L26T_A0 L26C_A0 -- L27T_A0 L27C_A0 L28T_A0 L28C_A0 L29T_A0 L29C_A0 L30T_D0 L30C_D0 -- L31T_A0 L31C_A0 L32T_A0 L32C_A0 L33T_A0 L33C_A0 L34T_A0 L34C_A0 L35T_D0 L35C_D0 L36T_A0 L36C_A0 L37T_A0 L37C_A0 L1T_D0 L1C_D0 -- L2T_A0 L2C_A0 L3T_A0 L3C_A0 L4T_D0 L4C_D0 -- L5T_A0 L5C_A0 75
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 P14 AN20 AM20 AK17 AL18 AL11 AP22 AN21 AM22 AM21 AP23 AN22 AL19 AK18 P15 AP24 AN23 AP25 AP26 AL13 AL20 AK19 AK20 AL21 P20 AN24 AM23 AN26 AN25 AL15 AK21 AL22 AM24 AL23 P21 AP27 AN27 AL24 AM25 AN13 AP28 AP29 76 VDDIO Bank -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) VREF Group -- 2 2 2 2 -- 2 2 2 2 3 3 3 3 -- 3 3 3 3 -- 3 3 3 3 -- 4 4 4 4 -- 4 4 4 4 -- 5 5 5 5 -- 5 5 I/O VSS IO IO IO IO VDDIO5 IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDDIO5 IO IO Pin Description VSS PB19C PB19D PB20A PB20B VDDIO5 PB20C PB20D PB21A PB21B PB21C PB21D PB22A PB22B VSS PB22C PB22D PB23A PB23B VDDIO5 PB23C PB23D PB24A PB24B VSS PB24C PB24D PB25A PB25B VDDIO5 PB25C PB25D PB26A PB26B VSS PB26C PB26D PB27A PB27B VDDIO5 PB27C PB27D Additional Function -- PBCK0T PBCK0C -- -- -- VREF_5_02 -- -- -- -- VREF_5_03 -- -- -- -- -- -- -- -- PBCK1T PBCK1C -- -- -- -- -- -- -- -- -- VREF_5_04 -- -- -- -- VREF_5_05 -- -- -- -- -- BM680 Pair -- L6T_A0 L6C_A0 L7T_D0 L7C_D0 -- L8T_D0 L8C_D0 L9T_A0 L9C_A0 L10T_D0 L10C_D0 L11T_D0 L11C_D0 -- L12T_D0 L12C_D0 L13T_A0 L13C_A0 -- L14T_D0 L14C_D0 L15T_D0 L15C_D0 -- L16T_D0 L16C_D0 L17T_A0 L17C_A0 -- L18T_D0 L18C_D0 L19T_D0 L19C_D0 -- L20T_A0 L20C_A0 L21T_D0 L21C_D0 -- L22T_A0 L22C_A0 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AN29 P22 AM27 AN28 AM26 AK22 AK23 AL25 R13 AP30 AP31 AK24 AN15 AM29 AM28 AN30 R14 AK25 AL26 AN17 AL27 AL28 AN31 R15 AK26 AM30 AL29 AK27 R20 AL30 AK29 AK28 AA16 AP32 AP33 AN32 AM31 AA17 AM32 AL31 AM33 AA18 VDDIO Bank 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- -- -- -- -- -- -- -- -- -- -- VREF Group 6 -- 6 6 6 6 6 7 -- 7 7 7 -- 7 7 7 -- 7 7 -- 8 8 8 -- 8 9 9 9 -- 9 9 -- -- -- -- -- -- -- -- -- -- -- I/O IO VSS IO IO IO IO IO IO VSS IO IO IO VDDIO5 IO IO IO VSS IO IO VDDIO5 IO IO IO VSS IO IO IO IO VSS IO IO VDD33 VDD15 IO IO IO IO VDD15 VDD33 IO IO VDD15 Pin Description PB28B VSS PB28C PB28D PB29B PB29C PB29D PB30B VSS PB30C PB30D PB31B VDDIO5 PB31C PB31D PB32B VSS PB32C PB32D VDDIO5 PB33C PB33D PB34B VSS PB34D PB35B PB35D PB36B VSS PB36C PB36D VDD33 VDD15 PSCHAR_LDIO9 PSCHAR_LDIO8 PSCHAR_LDIO7 PSCHAR_LDIO6 VDD15 VDD33 PSCHAR_LDIO5 PSCHAR_LDIO4 VDD15 Additional Function -- -- -- VREF_5_06 -- -- -- -- -- -- -- -- -- VREF_5_07 -- -- -- -- -- -- -- VREF_5_08 -- -- -- -- VREF_5_09 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- L23T_D0 L23C_D0 -- L24T_A0 L24C_A0 -- -- L25T_A0 L25C_A0 -- -- L26T_A0 L26C_A0 -- -- L27T_D0 L27C_D0 -- L28T_A0 L28C_A0 -- -- -- -- -- -- -- L29T_D0 L29C_D0 -- -- -- -- -- -- -- -- -- -- -- 77
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AK30 AL32 AA19 AB16 AK31 AJ30 AK33 AK34 AJ31 AJ33 AJ34 AH30 AH31 AH32 AH33 AH34 AA32 AF30 AF31 AE30 AE31 AB32 AD30 AD32 AF33 AC32 AF34 AE32 AD31 K32 AC30 AE33 AF32 AE34 AC30 AG30 AB30 AD33 AG31 AD34 AC31 AB31 78 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O IO IO VDD15 VDD15 VDD33 IO IO IO IO IO IO IO IO I VSSGB_B VDDGB_B VDDR O O I I VSST VDDIB VDDR I VSST I VDDR VSSRX VDDR VDDOB O VSST O VDDOB VSST VDDIB I VSST I VSSRX VDDOB Pin Description PSCHAR_LDIO3 PSCHAR_LDIO2 VDD15 VDD15 VDD33 PSCHAR_LDIO1 PSCHAR_LDIO0 PSCHAR_CKIO1 PSCHAR_CKIO0 PSCHAR_XCK PSCHAR_WDSYNC PSCHAR_CV PSCHAR_BYTSYNC ATMOUT_B VSSGB_B VDDGB_B VDDAUX_B REXT_B REXTN_B REFCLKN_B REFCLKP_B VSSAUX_B VDDIB_BA VDDRX_BA HDINN_BA VSSIB_BA HDINP_BA VDDRX_BA VSSRX_BA VDDTX_BA VDDOB_BA HDOUTN_BA VSSOB_BA HDOUTP_BA VDDOB_BA VSSTX_BA VDDIB_BB HDINN_BB VSSIB_BB HDINP_BB VSSRX_BB VDDOB_BB Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AC33 AG32 AC34 AB31 AG33 AA30 AB33 AG34 AB34 AA31 Y30 AA33 H30 AA34 Y31 H31 W30 Y33 H32 Y34 W31 V30 W33 H33 W34 V31 H34 J32 U31 T34 M32 T33 U30 T31 R34 N32 R33 T30 U32 R31 P34 U33 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O VSST O VDDOB VSST VDDIB I VSST I VSSRX VDDOB O VSST O VDDOB VSST VDDIB I VSST I VSSRX VDDOB O VSST O VDDOB VSST VSST VDDOB O VSST O VDDOB VSSRX I VSST I VDDIB VSST VDDOB O VSST Pin Description HDOUTN_BB VSSOB_BB HDOUTP_BB VDDOB_BB VSSTX_BB VDDIB_BC HDINN_BC VSSIB_BC HDINP_BC VSSRX_BC VDDOB_BC HDOUTN_BC VSSOB_BC HDOUTP_BC VDDOB_BC VSSTX_BC VDDIB_BD HDINN_BD VSSIB_BD HDINP_BD VSSRX_BD VDDOB_BD HDOUTN_BD VSSOB_BD HDOUTP_BD VDDOB_BD VSSTX_BD VSSTX_AD VDDOB_AD HDOUTP_AD VSSOB_AD HDOUTN_AD VDDOB_AD VSSRX_AD HDINP_AD VSSIB_AD HDINN_AD VDDIB_AD VSSTX_AC VDDOB_AC HDOUTP_AC VSSOB_AC Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 79
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 P33 R30 P31 N34 U34 N33 P30 V32 N31 M34 V33 M33 N31 M31 L34 V34 L33 N30 M30 K34 K33 M30 L32 L31 P32 J34 J33 R32 L30 K31 K30 J31 J30 Y32 G34 G33 G32 G31 F33 G30 F31 F30 80 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O VDDOB VSSRX I VSST I VDDIB VSST VDDOB O VSST O VDDOB VSSRX I VSST I VDDIB VDDOB O O VDDOB VDDR VSSRX VDDR I I VDDR VDDIB I I O O VDDR VDDGB_A VSSGB_A I I I I O I Pin Description HDOUTN_AC VDDOB_AC VSSRX_AC HDINP_AC VSSIB_AC HDINN_AC VDDIB_AC VSSTX_AB VDDOB_AB HDOUTP_AB VSSOB_AB HDOUTN_AB VDDOB_AB VSSRX_AB HDINP_AB VSSIB_AB HDINN_AB VDDIB_AB VDDOB_AA HDOUTP_AA HDOUTN_AA VDDOB_AA VDDTX_AA VSSRX_AA VDDRX_AA HDINP_AA HDINN_AA VDDRX_AA VDDIB_AA REFCLKP_A REFCLKN_A REXTN_A REXT_A VDDAUX_A VDDGB_A VSSGB_A ATMOUT_A PRESERVE01 PRESERVE02 PRESERVE03 PSYS_RSSIG_ALL PSYS_DOBISTN Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 E31 AB17 AB18 D32 E30 AB19 D31 C32 C31 AJ32 B32 A33 B31 A32 AK32 AB21 A31 B30 AB22 C30 D30 B13 E29 E28 AN33 D29 B29 C29 B15 E27 E26 AP34 A30 A29 E25 B17 E24 B28 C28 B2 D28 C27 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7 -- 7 7 -- 7 7 -- 8 8 8 -- 8 8 -- 8 9 9 -- 9 9 9 -- 9 9 I/O VDD33 VDD15 VDD15 I I VDD15 I I VDD33 VDD15 I I I I VDD15 VSS VDD33 IO VSS IO IO VDDIO1 IO IO VSS IO IO IO VDDIO1 IO IO Vss IO IO IO VDDIO1 IO IO IO Vss IO IO Pin Description VDD33 VDD15 VDD15 PBIST_TEST_ENN PLOOP_TEST_ENN VDD15 PASB_PDN PMP_TESTCLK VDD33 VDD15 PASB_RESETN PASB_TRISTN PMP_TESTCLK_ENN PASB_TESTCLK VDD15 VSS VDD33 PT36D VSS PT36B PT35D VDDIO1 PT35B PT34D Vss PT34B PT33D PT33C VDDIO1 PT32D PT32C Vss PT32B PT31D PT31C VDDIO1 PT31A PT30D PT30C Vss PT30A PT29D Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_07 -- -- -- VREF_1_08 -- -- -- -- -- -- VREF_1_09 -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 -- -- L3C_D3 L3T_D3 -- -- L4C_A0 L4T_A0 -- -- L5C_A0 81
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 D27 E23 E22 D26 D25 B33 D24 D23 C26 C25 D11 E21 E20 D22 D21 E34 A28 B26 B25 D13 B27 A27 A26 N13 C24 C22 C23 D15 B24 D20 D19 N14 E19 E18 C21 C20 A25 A24 B23 A23 N15 E17 82 VDDIO Bank 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) VREF Group 9 9 9 1 1 -- 1 1 1 1 -- 1 1 2 2 -- 2 2 2 -- 2 3 3 -- 3 3 3 -- 3 3 3 -- 3 3 4 4 4 4 4 4 -- 4 I/O IO IO IO IO IO Vss IO IO IO IO VDDIO1 IO IO IO IO Vss IO IO IO VDDIO1 IO IO IO Vss IO IO IO VDDIO1 IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO Pin Description PT29C PT29B PT29A PT28D PT28C Vss PT28B PT28A PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C Vss PT26B PT25D PT25C VDDIO1 PT25B PT24D PT24C Vss PT24B PT23D PT23C VDDIO1 PT23B PT22D PT22C Vss PT22B PT22A PT21D PT21C PT21B PT21A PT20D PT20C Vss PT20B Additional Function -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- -- VREF_1_03 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair L5T_A0 L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 L11C_A0 L11T_A0 -- -- L12C_A0 L12T_A0 -- -- L13C_A0 L13T_A0 -- -- L14C_A0 L14T_A0 -- -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 L17C_A0 L17T_A0 L18C_A0 L18T_A0 L19C_A0 L19T_A0 -- L20C_A0 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 E16 B22 B21 C18 C19 N20 A22 A21 N21 D17 D18 B20 B19 A20 A19 A18 B18 Y21 C17 D16 A17 B16 E15 E14 A16 A15 Y22 D14 C16 C15 D7 C14 B14 A14 A13 AA20 E12 E13 C13 C12 B12 A12 VDDIO Bank 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) VREF Group 4 4 4 4 4 -- 5 5 -- 5 5 5 5 5 5 5 5 -- 5 5 6 6 6 6 6 6 -- 6 1 1 -- 1 1 1 1 -- 2 2 2 2 2 2 I/O IO IO IO IO IO Vss IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO VDDIO0 IO IO IO IO Vss IO IO IO IO IO IO Pin Description PT20A PT19D PT19C PT19B PT19A Vss PT18D PT18C Vss PT18B PT18A PT17D PT17C PT17B PT17A PT16D PT16C Vss PT16B PT16A PT15D PT15C PT15B PT15A PT14D PT14C Vss PT14B PT13D PT13C VDDIO0 PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C PT11B PT11A Additional Function -- -- VREF_1_04 -- -- -- PTCK1C PTCK1T -- -- -- PTCK0C PTCK0T -- -- VREF_1_05 -- -- -- -- -- -- -- -- -- VREF_1_06 -- -- MPI_RTRY_N MPI_ACK_N -- -- VREF_0_01 M0 M1 -- MPI_CLK A21/MPI_BURST_N M2 M3 VREF_0_02 MPI_TEA_N BM680 Pair L20T_A0 L21C_A0 L21T_A0 L22C_A0 L22T_A0 -- L23C_A0 L23T_A0 -- L24C_A0 L24T_A0 L25C_A0 L25T_A0 L26C_A0 L26T_A0 L27C_A0 L27T_A0 -- L28C_D0 L28T_D0 L29C_D0 L29T_D0 L30C_A0 L30T_A0 L31C_A0 L31T_A0 -- -- L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 L5C_A0 L5T_A0 L6C_A0 L6T_A0 83
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 D12 C11 B11 A11 A10 AA21 B10 E11 D10 C10 A9 B9 AA22 E10 A8 B8 D9 C8 E9 D8 AB13 A7 A6 C7 B6 E8 E7 A5 B5 AB14 C6 D6 C4 B4 A4 A3 D5 E6 D4 E5 AB15 AL33 84 VDDIO Bank 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- -- -- -- -- -- VREF Group 3 3 3 3 3 -- 3 3 3 3 4 4 -- 4 4 4 4 4 5 5 -- 5 5 5 5 5 5 6 6 -- 6 6 6 6 6 6 -- -- -- -- -- -- I/O IO IO IO IO IO Vss IO IO IO IO IO IO Vss IO IO IO IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO O IO IO VDD33 Vss VDD15 Pin Description PT10D PT10C PT10B PT9D PT9C Vss PT9B PT8D PT8C PT8B PT7D PT7C Vss PT7B PT6D PT6C PT6B PT6A PT5D PT5C Vss PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C Vss PT3B PT3A PT2D PT2C PT2B PT2A PCFG_MPI_IRQ PCCLK PDONE VDD33 Vss VDD15 Additional Function -- -- -- VREF_0_03 -- -- -- D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 -- -- A18/MPI_TSZ0 D3 VREF_0_04 -- D1 D2 -- -- VREF_0_05 TDI TCK -- -- -- VREF_0_06 -- -- -- PLL_CK1C/PPLL PLL_CK1T/PPLL -- --
CFG_IRQ_N/MPI_IRQ_N
BM680 Pair L7C_D0 L7T_D0 -- L8C_A0 L8T_A0 -- -- L9C_D0 L9T_D0 -- L10C_A0 L10T_A0 -- -- L11C_A0 L11T_A0 L12C_D0 L12T_D0 L13C_D0 L13T_D0 -- L14C_A0 L14T_A0 L15C_D0 L15T_D0 L16C_A0 L16T_A0 L17C_A0 L17T_A0 -- L18C_A0 L18T_A0 L19C_A0 L19T_A0 L20C_A0 L20T_A0 -- -- -- -- -- --
CCLK DONE -- -- --
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 AL34 AM34 AN34 B34 C33 C34 D33 D34 E32 E33 F32 F34 N16 N17 N18 N19 P16 P17 P18 P19 R16 R17 R18 R19 T13 T14 T15 T20 T21 T22 U13 U14 U15 U20 U21 U22 V13 V14 V15 V20 V21 V22 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Pin Description VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 85
Agere Systems Inc.
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Pin Information (continued)
Table 27. ORT82G5 680-Pin PBGAM Pinout (continued) BM680 W13 W14 W15 W20 W21 W22 Y16 Y17 Y18 Y19 T32 W32 VDDIO Bank -- -- -- -- -- -- -- -- -- -- -- -- VREF Group -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC Pin Description VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC Additional Function -- -- -- -- -- -- -- -- -- -- -- -- BM680 Pair -- -- -- -- -- -- -- -- -- -- -- --
86
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: JC = ------------------The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
TJ - TC Q
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.): JA = ------------------TJ - TA Q
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/W.
JB
This is the thermal resistance from junction to board (JL). It is defined by: JB = ------------------TJ - TB Q
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W and that this parameter and the way it is measured are still in JEDEC committee.
JC FPSC Maximum Junction Temperature
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance and it is defined by:
TJ - TC JC = ------------------Q
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
Once the power dissipated by the FPSC has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA) Table 28 lists the thermal characteristics for all packages used with the ORCA ORT82G5 Series of FPSCs.
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Package Thermal Characteristics
Table 28. ORCA ORT82G5 Plastic Package Thermal Guidelines
JA (C/W)
Package 680-Pin PBGAM 0 fpm 9.8 200 fpm TBD 500 fpm TBD
T = 85C Max TJ = 125 C Max 0 fpm (W) 4.1
Note: The 680-pin PBGAM package for the ORT82G5 includes a heat spreader.
Package Coplanarity
The coplanarity limits of the Agere packages are as follows:
s
PBGAM: 8.0 mils
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 29 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m. The parasitic values in Table 29 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Table 29. ORCA ORT82G5 Package Parasitics Package Type 680-Pin PBGAM LSW 3.8 LMW 1.3
LSW PAD N
RW 250
RW
C1 1.0
LSL
C2 1.0
BOARD PAD
CM 0.3
LSL 2.8--5
LML 0.5--1
C1 LMW CM LML
C2
PAD N + 1 LSW RW C1 LSL C2
5-3862(C)r2
Figure 21. Package Parasitics 88 Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.
Agere Systems Inc.
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ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
Package Outline Diagrams (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00
+ 0.70
35.00
30.00 - 0.00
+ 0.70
1.170 0.61 0.06 SEATING PLANE 0.25 SOLDER BALL 0.50 0.10 33 SPACES @ 1.00 = 33.00 2.51 MAX
AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34
0.64 0.15
33 SPACES @ 1.00 = 33.00
A1 BALL CORNER
5-4406(F)
90
Agere Systems Inc.
Preliminary Data Sheet July 2001
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Hardware Ordering Information
ORT82G5 DEVICE TYPE SPEED GRADE
-2 BM 680 TEMPERATURE RANGE NUMBER OF PINS PACKAGE TYPE
5-6435(F)
Table 30. Device Type Options Device ORT82G5 Parameter Voltage Package Value 1.5 V core. 3.3 V/2.5 V I/O. 680-pin PBGAM.
Table 31. Temperature Options Symbol (Blank) Description Industrial Temperature -40 C to +85 C
Table 32. Package Type Options Symbol BM Description Plastic Ball Grid Array, Multilayer
Table 33. ORCA FPSC Package Matrix (Speed Grades)
Package
Device
680-Pin PBGAM BM680
ORT82G5
-1, -2, -3
Software Ordering Information
Implementing a design in an ORT82G5 requires the ORCA Foundry Development System and an ORT82G5 FPSC Design Kit. For ordering information, please visit: http://www.agere.com/micro/netcom/ipkits/ORT82G5/
Agere Systems Inc.
91
ORCA ORT82G5 FPSC Eight-Channel 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet July 2001
InfiniBand is a trademark of Infiniband Trade Association. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. PAL is a trademark of Advanced Micro Devices, Inc. PowerPC is a registered trademark of International Business Machines, Inc. AMBA is a trademark, and ARM is a registered trademark of Advanced RISC Machines Limited. Synopsys Smart Model is a registered trademark of Synopsys, Inc. Motorola is a registered trademark of Motorola, Inc. Firewire is a registered trademark of Apple Computer, Inc.
For additional information, contact your Agere Systems Account Manager or the following: http://www.agere.com or for FPGAs/FPSCs http://www.agere.com/orca INTERNET: docmaster@agere.com E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. ORCA is a registered trademark of Agere Systems Inc. Foundry is a trademark of Xilinx, Inc.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A.
July 2001 DS01-218NCIP

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